From: Jim MacArthur <jim.macarthur@linaro.org>
To: qemu-devel@nongnu.org
Cc: Jim MacArthur <jim.macarthur@linaro.org>
Subject: [PATCH 0/3] Basic ASID2 support
Date: Wed, 12 Nov 2025 09:17:49 +0000 [thread overview]
Message-ID: <20251112092048.450090-1-jim.macarthur@linaro.org> (raw)
Enable the ID_AA64MMFR4_EL1 register, add the ASID2 field for cpu_max,
then enable writes to FNG1, FNG0, and A2 bits of TCR2_EL1. Any change
of ASID still causes a TLB flush.
Jim MacArthur (3):
target/arm: Enable ID_AA64MMFR4_EL1 register.
target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2
tests: Add test for ASID2 and write/read of feature bits
target/arm/cpu-features.h | 7 +++++
target/arm/cpu-sysregs.h.inc | 1 +
target/arm/helper.c | 7 +++--
target/arm/tcg/cpu64.c | 4 +++
tests/tcg/aarch64/system/asid2.c | 53 ++++++++++++++++++++++++++++++++
5 files changed, 70 insertions(+), 2 deletions(-)
create mode 100644 tests/tcg/aarch64/system/asid2.c
--
2.43.0
next reply other threads:[~2025-11-12 9:23 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-12 9:17 Jim MacArthur [this message]
2025-11-12 9:17 ` [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur
2025-11-15 12:12 ` Richard Henderson
2025-11-12 9:17 ` [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 Jim MacArthur
2025-11-15 12:17 ` Richard Henderson
2025-11-12 9:17 ` [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur
2025-11-15 12:21 ` Richard Henderson
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