From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Max Chou <max.chou@sifive.com>
Subject: [PATCH v3 0/3] Fix some more RVV source overlap issues
Date: Fri, 14 Nov 2025 01:16:01 +0800 [thread overview]
Message-ID: <20251113171604.3034161-1-max.chou@sifive.com> (raw)
This patchset is based on the v2 with following update:
* Update the commit message to distinguish the affected rvv instructions.
Reference:
* v1: 20250415043207.3512209-1-antonb@tenstorrent.com
* v2: 20250627132022.439315-1-max.chou@sifive.com
Anton Blanchard (3):
target/riscv: rvv: Apply vext_check_input_eew to vector int/fp compare
instructions
target/riscv: rvv: Apply vext_check_input_eew to vector reduction
instructions
target/riscv: vadc and vsbc are vm=0 instructions
target/riscv/insn32.decode | 10 +++++-----
target/riscv/insn_trans/trans_rvv.c.inc | 26 ++++++++++++++-----------
2 files changed, 20 insertions(+), 16 deletions(-)
--
2.43.0
next reply other threads:[~2025-11-13 17:17 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-13 17:16 Max Chou [this message]
2025-11-13 17:16 ` [PATCH v3 1/3] target/riscv: rvv: Apply vext_check_input_eew to vector int/fp compare instructions Max Chou
2025-11-13 17:16 ` [PATCH v3 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions Max Chou
2025-11-13 17:16 ` [PATCH v3 3/3] target/riscv: vadc and vsbc are vm=0 instructions Max Chou
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