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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-bc375081023sm2712992a12.21.2025.11.13.09.16.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Nov 2025 09:16:12 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Anton Blanchard , Max Chou , Nutty Liu Subject: [PATCH v3 1/3] target/riscv: rvv: Apply vext_check_input_eew to vector int/fp compare instructions Date: Fri, 14 Nov 2025 01:16:02 +0800 Message-ID: <20251113171604.3034161-2-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251113171604.3034161-1-max.chou@sifive.com> References: <20251113171604.3034161-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=max.chou@sifive.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Anton Blanchard Handle the overlap of source registers with different EEWs for vector integer/floatint point comare instructions. Signed-off-by: Anton Blanchard Reviewed-by: Max Chou Reviewed-by: Nutty Liu Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 2a487179f63..422e1a21185 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -436,9 +436,10 @@ static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm) require_align(vs1, s->lmul); } -static bool vext_check_ms(DisasContext *s, int vd, int vs) +static bool vext_check_ms(DisasContext *s, int vd, int vs, int vm) { - bool ret = require_align(vs, s->lmul); + bool ret = require_align(vs, s->lmul) && + vext_check_input_eew(s, vs, s->sew, -1, 0, vm); if (vd != vs) { ret &= require_noover(vd, 0, vs, s->lmul); } @@ -461,9 +462,10 @@ static bool vext_check_ms(DisasContext *s, int vd, int vs) * with a mask value (e.g., comparisons) or the scalar result * of a reduction. (Section 5.3) */ -static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2) +static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2, int vm) { - bool ret = vext_check_ms(s, vd, vs2) && + bool ret = vext_check_ms(s, vd, vs2, vm) && + vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) && require_align(vs1, s->lmul); if (vd != vs1) { ret &= require_noover(vd, 0, vs1, s->lmul); @@ -1823,7 +1825,7 @@ static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && - vext_check_mss(s, a->rd, a->rs1, a->rs2); + vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm); } GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check) @@ -1859,7 +1861,7 @@ static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && - vext_check_ms(s, a->rd, a->rs2); + vext_check_ms(s, a->rd, a->rs2, a->vm); } GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check) @@ -2033,7 +2035,7 @@ static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && - vext_check_mss(s, a->rd, a->rs1, a->rs2); + vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm); } GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check) @@ -2047,7 +2049,7 @@ static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && - vext_check_ms(s, a->rd, a->rs2); + vext_check_ms(s, a->rd, a->rs2, a->vm); } GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check) @@ -2755,7 +2757,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s) && - vext_check_mss(s, a->rd, a->rs1, a->rs2); + vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm); } GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check) @@ -2768,7 +2770,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s) && - vext_check_ms(s, a->rd, a->rs2); + vext_check_ms(s, a->rd, a->rs2, a->vm); } GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check) -- 2.43.0