* [PATCH v3 1/3] target/riscv: rvv: Apply vext_check_input_eew to vector int/fp compare instructions
2025-11-13 17:16 [PATCH v3 0/3] Fix some more RVV source overlap issues Max Chou
@ 2025-11-13 17:16 ` Max Chou
2025-11-13 17:16 ` [PATCH v3 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions Max Chou
2025-11-13 17:16 ` [PATCH v3 3/3] target/riscv: vadc and vsbc are vm=0 instructions Max Chou
2 siblings, 0 replies; 4+ messages in thread
From: Max Chou @ 2025-11-13 17:16 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anton Blanchard, Max Chou,
Nutty Liu
From: Anton Blanchard <antonb@tenstorrent.com>
Handle the overlap of source registers with different EEWs for vector
integer/floatint point comare instructions.
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 2a487179f63..422e1a21185 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -436,9 +436,10 @@ static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
require_align(vs1, s->lmul);
}
-static bool vext_check_ms(DisasContext *s, int vd, int vs)
+static bool vext_check_ms(DisasContext *s, int vd, int vs, int vm)
{
- bool ret = require_align(vs, s->lmul);
+ bool ret = require_align(vs, s->lmul) &&
+ vext_check_input_eew(s, vs, s->sew, -1, 0, vm);
if (vd != vs) {
ret &= require_noover(vd, 0, vs, s->lmul);
}
@@ -461,9 +462,10 @@ static bool vext_check_ms(DisasContext *s, int vd, int vs)
* with a mask value (e.g., comparisons) or the scalar result
* of a reduction. (Section 5.3)
*/
-static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2)
+static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2, int vm)
{
- bool ret = vext_check_ms(s, vd, vs2) &&
+ bool ret = vext_check_ms(s, vd, vs2, vm) &&
+ vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
require_align(vs1, s->lmul);
if (vd != vs1) {
ret &= require_noover(vd, 0, vs1, s->lmul);
@@ -1823,7 +1825,7 @@ static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
vext_check_isa_ill(s) &&
- vext_check_mss(s, a->rd, a->rs1, a->rs2);
+ vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
}
GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
@@ -1859,7 +1861,7 @@ static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
vext_check_isa_ill(s) &&
- vext_check_ms(s, a->rd, a->rs2);
+ vext_check_ms(s, a->rd, a->rs2, a->vm);
}
GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
@@ -2033,7 +2035,7 @@ static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
vext_check_isa_ill(s) &&
- vext_check_mss(s, a->rd, a->rs1, a->rs2);
+ vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
}
GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
@@ -2047,7 +2049,7 @@ static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
vext_check_isa_ill(s) &&
- vext_check_ms(s, a->rd, a->rs2);
+ vext_check_ms(s, a->rd, a->rs2, a->vm);
}
GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
@@ -2755,7 +2757,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
- vext_check_mss(s, a->rd, a->rs1, a->rs2);
+ vext_check_mss(s, a->rd, a->rs1, a->rs2, a->vm);
}
GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -2768,7 +2770,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
return require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s) &&
- vext_check_ms(s, a->rd, a->rs2);
+ vext_check_ms(s, a->rd, a->rs2, a->vm);
}
GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
--
2.43.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v3 2/3] target/riscv: rvv: Apply vext_check_input_eew to vector reduction instructions
2025-11-13 17:16 [PATCH v3 0/3] Fix some more RVV source overlap issues Max Chou
2025-11-13 17:16 ` [PATCH v3 1/3] target/riscv: rvv: Apply vext_check_input_eew to vector int/fp compare instructions Max Chou
@ 2025-11-13 17:16 ` Max Chou
2025-11-13 17:16 ` [PATCH v3 3/3] target/riscv: vadc and vsbc are vm=0 instructions Max Chou
2 siblings, 0 replies; 4+ messages in thread
From: Max Chou @ 2025-11-13 17:16 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anton Blanchard, Nutty Liu,
Max Chou
From: Anton Blanchard <antonb@tenstorrent.com>
Handle the overlap of source registers with different EEWs for vector
reduction instructions.
Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 422e1a21185..2d9cf27ef76 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3076,6 +3076,7 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
vext_check_isa_ill(s) &&
+ vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) &&
vext_check_reduction(s, a->rs2);
}
@@ -3092,7 +3093,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
{
return reduction_check(s, a) && (s->sew < MO_64) &&
- ((s->sew + 1) <= (s->cfg_ptr->elen >> 4));
+ ((s->sew + 1) <= (s->cfg_ptr->elen >> 4)) &&
+ vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew + 1, a->vm);
}
GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
--
2.43.0
^ permalink raw reply related [flat|nested] 4+ messages in thread