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Sun, 16 Nov 2025 17:40:46 -0800 (PST) Received: from [10.0.0.22] ([185.213.193.149]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee1c21ea34sm18246551cf.30.2025.11.16.17.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Nov 2025 17:40:45 -0800 (PST) From: Gabriel Brookman Date: Sun, 16 Nov 2025 20:40:22 -0500 Subject: [PATCH RFC v2 05/10] tests/tcg: added test for MTE write-only MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251116-feat-mte4-v2-5-9a7122b7fa76@gmail.com> References: <20251116-feat-mte4-v2-0-9a7122b7fa76@gmail.com> In-Reply-To: <20251116-feat-mte4-v2-0-9a7122b7fa76@gmail.com> To: qemu-devel@nongnu.org Cc: Peter Maydell , Gustavo Romero , qemu-arm@nongnu.org, Gabriel Brookman X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763343639; l=2569; i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id; bh=+MW5eKyHmFp9lQRa143T4qRhRjYlTU7oYxdQCpWyD18=; b=uq6fD+kwIaV7oIcJ/6+wobrRZ3ZDAit3vkKR+4CyEE3dVUnUzdHKyJYPOiWb6+WGm3DJU9Iu1 suPPYK3TXXGD/pP2BKcd38STp/lE7osYumWOG3yElWxFbokONjUy6/1 X-Developer-Key: i=brookmangabriel@gmail.com; a=ed25519; pk=m9TtPDal6WzoHNnQiHHKf8dTrv3DUCPUUTujuo8vNrw= Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=brookmangabriel@gmail.com; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This test cannot be run in user-mode because the control bit that enables this feature is only writable at EL1. Signed-off-by: Gabriel Brookman --- tests/tcg/aarch64/Makefile.target | 2 +- tests/tcg/aarch64/mte-10.c | 55 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 1 deletion(-) diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index b491cfb5e1..6203ac9b51 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -64,7 +64,7 @@ AARCH64_TESTS += bti-2 # MTE Tests ifneq ($(CROSS_CC_HAS_ARMV8_MTE),) -AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7 mte-8 mte-9 +AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7 mte-8 mte-9 mte-10 mte-%: CFLAGS += $(CROSS_CC_HAS_ARMV8_MTE) endif diff --git a/tests/tcg/aarch64/mte-10.c b/tests/tcg/aarch64/mte-10.c new file mode 100644 index 0000000000..0fa3f97e1d --- /dev/null +++ b/tests/tcg/aarch64/mte-10.c @@ -0,0 +1,55 @@ +/* + * Memory tagging, write-only tag checking + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +void pass(int sig, siginfo_t *info, void *uc) +{ + exit(0); +} + +int main(int ac, char **av) +{ + struct sigaction sa; + int *p0, *p1, *p2; + long excl = 1; + + /* + * NOTE FOR REVIEWERS: to run this test locally, I modified + * enable_mte to also activate write-only tag checking by writing + * to ID_AA64PFR2_EL1. I am not sure how to modify the test so that + * it works without that modification. Input appreciated. + */ + enable_mte(PR_MTE_TCF_SYNC); + p0 = alloc_mte_mem(sizeof(*p0)); + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg %0, [%0]" : : "r"(p1)); + + /* + * We write to p1 (stg above makes this check pass) and read from + * p2 (improperly tagged, but since it's a read, we don't care). + */ + *p1 = *p2; + + /* enable handler */ + memset(&sa, 0, sizeof(sa)); + sa.sa_sigaction = pass; + sa.sa_flags = SA_SIGINFO; + sigaction(SIGSEGV, &sa, NULL); + + /* now we write to badly checked p2, should fault. */ + *p2 = 0; + + abort(); +} -- 2.51.2