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Sun, 16 Nov 2025 17:40:47 -0800 (PST) Received: from [10.0.0.22] ([185.213.193.149]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4ee1c21ea34sm18246551cf.30.2025.11.16.17.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Nov 2025 17:40:46 -0800 (PST) From: Gabriel Brookman Date: Sun, 16 Nov 2025 20:40:23 -0500 Subject: [PATCH RFC v2 06/10] target/arm: add canonical and no-address tag logic MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251116-feat-mte4-v2-6-9a7122b7fa76@gmail.com> References: <20251116-feat-mte4-v2-0-9a7122b7fa76@gmail.com> In-Reply-To: <20251116-feat-mte4-v2-0-9a7122b7fa76@gmail.com> To: qemu-devel@nongnu.org Cc: Peter Maydell , Gustavo Romero , qemu-arm@nongnu.org, Gabriel Brookman X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1763343639; l=3340; i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id; bh=F2pGZprB8kCYpSFO6b+fLbFMcjK4Pgwg8dscgoUacB0=; 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Described in the ARM ARM section "Logical Address Tagging". Signed-off-by: Gabriel Brookman --- target/arm/internals.h | 40 ++++++++++++++++++++++++++++++++++++++++ target/arm/tcg/mte_helper.c | 12 ++++++++++++ 2 files changed, 52 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index 75677945af..5f0bcdaaac 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1633,6 +1633,46 @@ static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag) return tcma && match; } +/* Return whether or not the second nibble of a VA matches bit 55. */ +static inline bool tag_is_canonical(int ptr_tag, int bit55) +{ + return ((ptr_tag + bit55) & 0xf) == 0; +} + +/* Return true if mtx bits mean that the access is canonically checked. */ +static inline bool mtx_check(CPUARMState *env, bool bit55) +{ + /* + * the MTX bits used in EL0 are those used in whichever EL is used + * for the supervisor. The EL that contains the supervisor uses + * bits 60 and 61 (MTX0 and MTX1), while the other ELs that aren't + * used by the supervisor. + */ + int el = arm_current_el(env); + if (el == 0) { + if (HCR_E2H & env->cp15.hcr_el2) { + return (1l << (60 + bit55)) & env->cp15.tcr_el[2]; + } else { + return (1l << (60 + bit55)) & env->cp15.tcr_el[1]; + } + } else if (el == 1) { + if (HCR_E2H & env->cp15.hcr_el2) { + g_assert_not_reached(); + } else { + return (1l << (60 + bit55)) & env->cp15.tcr_el[1]; + } + } else if (el == 2) { + if (HCR_E2H & env->cp15.hcr_el2) { + return (1l << (60 + bit55)) & env->cp15.tcr_el[2]; + } else { + return (1l << 33) & env->cp15.tcr_el[2]; + } + } else if (el == 3) { + return (1l << 33) & env->cp15.tcr_el[3]; + } + return false; +} + /* * For TBI, ideally, we would do nothing. Proper behaviour on fault is * for the tag to be present in the FAR_ELx register. But for user-only diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index f9fd6fd408..513ee8d6a1 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -799,6 +799,10 @@ static int mte_probe_int(CPUARMState *env, uint32_t desc, uint64_t ptr, return 1; } + if (mtx_check(env, bit55)) { + return tag_is_canonical(ptr_tag, bit55); + } + mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD; sizem1 = FIELD_EX32(desc, MTEDESC, SIZEM1); @@ -962,6 +966,14 @@ uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t ptr) goto done; } + if (mtx_check(env, bit55)) { + if (tag_is_canonical(ptr_tag, bit55)) { + goto done; + } + mte_check_fail(env, desc, ptr, ra); + } + + /* * In arm_cpu_realizefn, we asserted that dcz > LOG2_TAG_GRANULE+1, * i.e. 32 bytes, which is an unreasonably small dcz anyway, to make -- 2.51.2