From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED5F2CEBF93 for ; Mon, 17 Nov 2025 09:41:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vKvhr-0004bw-4a; Mon, 17 Nov 2025 04:39:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vKvhb-0004XR-Qf for qemu-devel@nongnu.org; Mon, 17 Nov 2025 04:39:17 -0500 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vKvhZ-0006HR-DL for qemu-devel@nongnu.org; Mon, 17 Nov 2025 04:39:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763372353; x=1794908353; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OF+vzJLCAHqZO5/sSzcok+C/XvWYe1dLyHkysStEf5g=; b=kiVnnigv8JuzNh4bTHihJNnecHZiFIFiwLM1Hjt4pH7NE1BJyRdy5DL7 Fk3ZiLgDvGVlsxxsJp/JvlrKK2agDzbBUVHdwZB2Qfw0PNMuTXPiy8xaI 1oaZMc0N/1lQ9Fu6EQF7/QE1r8MXUbfzChzANJ5ZlgM1e66k0W1pv2mCG yFdZKEvwnImZSDfsTnaNX5/YnGcTQuMw4xzdZzd1B3IWOwqC/KcafTv2k agMP5zJUbJx2MARtF7iE8gB+h91K50emQqb1AyoFQVVzM0QoxrYTIUAyp 2FUrmiUV7N4y9Z7Ifh96lu3a18rj83I02Fmis2FUjkZcUk/0REgNtWpzL w==; X-CSE-ConnectionGUID: aG7ZZkC7QcKTI2ZPMxhsGQ== X-CSE-MsgGUID: sYhi+tyUR4GNxvcBlSlcVw== X-IronPort-AV: E=McAfee;i="6800,10657,11615"; a="76045981" X-IronPort-AV: E=Sophos;i="6.19,311,1754982000"; d="scan'208";a="76045981" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 01:39:13 -0800 X-CSE-ConnectionGUID: mQdwXzMdQ5WfKUk+8iB+OA== X-CSE-MsgGUID: a9rfdm5dRjmR0InUSN/+zA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,311,1754982000"; d="scan'208";a="190070924" Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 01:39:09 -0800 From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v8 10/23] intel_iommu_accel: Fail passthrough device under PCI bridge if x-flts=on Date: Mon, 17 Nov 2025 04:37:13 -0500 Message-ID: <20251117093729.1121324-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20251117093729.1121324-1-zhenzhong.duan@intel.com> References: <20251117093729.1121324-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently we don't support nested translation for passthrough device with emulated device under same PCI bridge, because they require different address space when x-flts=on. In theory, we do support if devices under same PCI bridge are all passthrough devices. But emulated device can be hotplugged under same bridge. To simplify, just forbid passthrough device under PCI bridge no matter if there is, or will be emulated devices under same bridge. This is acceptable because PCIE bridge is more popular than PCI bridge now. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_accel.h | 4 ++-- hw/i386/intel_iommu.c | 7 ++++--- hw/i386/intel_iommu_accel.c | 12 +++++++++++- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index c5274e342c..7ebf137a1a 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -13,11 +13,11 @@ #include CONFIG_DEVICES #ifdef CONFIG_VTD_ACCEL -bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUDevice *hiod, +bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, - HostIOMMUDevice *hiod, + VTDHostIOMMUDevice *vtd_hiod, Error **errp) { error_setg(errp, diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index d3c8a75878..4ebf56a74f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4571,9 +4571,10 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, return vtd_dev_as; } -static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, +static bool vtd_check_hiod(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp) { + HostIOMMUDevice *hiod = vtd_hiod->hiod; HostIOMMUDeviceClass *hiodc = HOST_IOMMU_DEVICE_GET_CLASS(hiod); int ret; @@ -4597,7 +4598,7 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, return true; } - return vtd_check_hiod_accel(s, hiod, errp); + return vtd_check_hiod_accel(s, vtd_hiod, errp); } static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, @@ -4633,7 +4634,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, vtd_hiod->iommu_state = s; vtd_hiod->hiod = hiod; - if (!vtd_check_hiod(s, hiod, errp)) { + if (!vtd_check_hiod(s, vtd_hiod, errp)) { g_free(vtd_hiod); vtd_iommu_unlock(s); return false; diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 6846c6ec4d..ead6c42879 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -12,12 +12,16 @@ #include "system/iommufd.h" #include "intel_iommu_internal.h" #include "intel_iommu_accel.h" +#include "hw/pci/pci_bus.h" -bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUDevice *hiod, +bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp) { + HostIOMMUDevice *hiod = vtd_hiod->hiod; struct HostIOMMUDeviceCaps *caps = &hiod->caps; struct iommu_hw_info_vtd *vtd = &caps->vendor_caps.vtd; + PCIBus *bus = vtd_hiod->bus; + PCIDevice *pdev = bus->devices[vtd_hiod->devfn]; if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) { error_setg(errp, "Need IOMMUFD backend when x-flts=on"); @@ -36,6 +40,12 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUDevice *hiod, return false; } + if (pci_device_get_iommu_bus_devfn(pdev, &bus, NULL, NULL)) { + error_setg(errp, "Host device downstream to a PCI bridge is " + "unsupported when x-flts=on"); + return false; + } + error_setg(errp, "host IOMMU is incompatible with guest first stage translation"); return false; -- 2.47.1