From: Zhao Liu <zhao1.liu@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org, Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH 0/2] i386/cpu: Correct comments for CPUID 0x1D and 0x1E
Date: Tue, 18 Nov 2025 16:08:35 +0800 [thread overview]
Message-ID: <20251118080837.837505-1-zhao1.liu@intel.com> (raw)
Hi,
CPUID 0x1D and 0x1E are marked as hardcoded for Sapphire Rapids and
there's the previous attempt [*] to make the fields in 0x1D.0x1 and
0x1E.0x0.EBX user-configurable.
In fact, the "hardcoded" values are defined for architecture, not
the SPR-specific thing, so that it's incorrect and unnecessary to make
them user-configurable.
Therefore, drop the incorrect and misleading comments.
[*]: https://lore.kernel.org/qemu-devel/20230106083826.5384-2-lei4.wang@intel.com/
Thanks and Best Regards,
Zhao
---
Zhao Liu (2):
i386/cpu: Drop incorrect comment for CPUID 0x1D
i386/cpu: Drop incorrect comment for CPUID 0x1E
target/i386/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--
2.34.1
next reply other threads:[~2025-11-18 7:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-18 8:08 Zhao Liu [this message]
2025-11-18 8:08 ` [PATCH 1/2] i386/cpu: Drop incorrect comment for CPUID 0x1D Zhao Liu
2025-11-18 9:12 ` Xiaoyao Li
2025-11-18 8:08 ` [PATCH 2/2] i386/cpu: Drop incorrect comment for CPUID 0x1E Zhao Liu
2025-11-18 9:16 ` Xiaoyao Li
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