* [PATCH 01/10] i386/cpu: Add support for MOVRS in CPUID enumeration
2025-11-20 7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
@ 2025-11-20 7:10 ` Zhao Liu
2025-11-20 7:10 ` [PATCH 02/10] i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions Zhao Liu
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-11-20 7:10 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé; +Cc: qemu-devel, Xudong Hao, Zhao Liu
MOVRS is a new set of instructions introduced in the Intel platform
Diamond Rapids, to load instructions that carry a read-shared hint.
Functionally, MOVRS family is equivalent to existing load instructions,
but its read-shared hint indicates the source memory location is likely
to become read-shared by multiple processors, i.e., read in the future
by at least one other processor before it is written (assuming it is
ever written in the future). It could optimize the behavior of the
caches, especially shared caches, for this data for future reads by
multiple processors. Additionally, MOVRS family also includes a software
prefetch instruction, PREFETCHRST2, that carries the same read-shared
hint. [*]
MOVRS family is enumerated by CPUID single-bit (0x7.0x1.EAX[bit 31]).
Add its enumeration support.
[*]: Intel Architecture Instruction Set Extensions and Future Features
(rev.059).
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Reference link: https://cdrdv2.intel.com/v1/dl/getContent/865891
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0c954202cea8..1aae9cba13af 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1266,7 +1266,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, "fred", "lkgs", "wrmsrns",
NULL, "amx-fp16", NULL, "avx-ifma",
NULL, NULL, "lam", NULL,
- NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, "movrs",
},
.cpuid = {
.eax = 7,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d15a89f8c72e..7b50c0c04f6e 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1030,6 +1030,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
#define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
/* Linear Address Masking */
#define CPUID_7_1_EAX_LAM (1U << 26)
+/* MOVRS Instructions */
+#define CPUID_7_1_EAX_MOVRS (1U << 31)
/* The immediate form of MSR access instructions */
#define CPUID_7_1_ECX_MSR_IMM (1U << 5)
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 02/10] i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions
2025-11-20 7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
2025-11-20 7:10 ` [PATCH 01/10] i386/cpu: Add support for MOVRS in CPUID enumeration Zhao Liu
@ 2025-11-20 7:10 ` Zhao Liu
2025-11-20 7:10 ` [PATCH 03/10] i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration Zhao Liu
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-11-20 7:10 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé; +Cc: qemu-devel, Xudong Hao, Zhao Liu
Intel Diamond Rapids adds new AMX instructions to support new formats
and memory operations [*]. And it introduces the CPUID subleaf 0x1E.0x1
to centralize the discrete AMX feature bits within EAX.
For new feature bits (CPUID 0x1E.0x1.EAX[bits 4,6-8]), it's
straightforward to add their enurmeration support.
In addition to the new features, CPUID 0x1E.0x1.EAX[bits 0-3] are
mirrored positions of existing AMX feature bits distributing across
the 0x7 leaves. It's not flexible to make these mirror bits have the
same names as existing ones, because QEMU would try to set both original
bit and mirror bit which would cause warning if host doesn't support
0x1E.0x1 subleaf. Thus, name these mirror bits with "*-mirror" suffix.
[*]: Intel Architecture Instruction Set Extensions and Future Features
(rev.059).
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Reference link: https://cdrdv2.intel.com/v1/dl/getContent/865891
---
target/i386/cpu.c | 25 +++++++++++++++++++++++++
target/i386/cpu.h | 18 ++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1aae9cba13af..1985a6b3b835 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1037,6 +1037,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
#define TCG_SGX_12_1_EAX_FEATURES 0
#define TCG_24_0_EBX_FEATURES 0
#define TCG_29_0_EBX_FEATURES 0
+#define TCG_1E_1_EAX_FEATURES 0
#if defined CONFIG_USER_ONLY
#define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \
@@ -1332,6 +1333,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = TCG_7_2_EDX_FEATURES,
},
+ [FEAT_1E_1_EAX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "amx-int8-mirror", "amx-bf16-mirror", "amx-complex-mirror", "amx-fp16-mirror",
+ "amx-fp8", NULL, "amx-tf32", "amx-avx512",
+ "amx-movrs", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = {
+ .eax = 0x1e,
+ .needs_ecx = true, .ecx = 1,
+ .reg = R_EAX,
+ },
+ .tcg_features = TCG_1E_1_EAX_FEATURES,
+ },
[FEAT_24_0_EBX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
@@ -8413,8 +8433,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
}
if (count == 0) {
+ uint32_t unused;
+ x86_cpu_get_supported_cpuid(0x1E, 0, eax, &unused,
+ &unused, &unused);
/* Highest numbered palette subleaf */
*ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8);
+ } else if (count == 1) {
+ *eax = env->features[FEAT_1E_1_EAX];
}
break;
}
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7b50c0c04f6e..df57b41567eb 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -698,6 +698,7 @@ typedef enum FeatureWord {
FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */
FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */
FEAT_29_0_EBX, /* CPUID[EAX=0x29,ECX=0].EBX */
+ FEAT_1E_1_EAX, /* CPUID[EAX=0x1E,ECX=1].EAX */
FEATURE_WORDS,
} FeatureWord;
@@ -1071,6 +1072,23 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
/* Packets which contain IP payload have LIP values */
#define CPUID_14_0_ECX_LIP (1U << 31)
+/* AMX_INT8 instruction (mirror of CPUID_7_0_EDX_AMX_INT8) */
+#define CPUID_1E_1_EAX_AMX_INT8_MIRROR (1U << 0)
+/* AMX_BF16 instruction (mirror of CPUID_7_0_EDX_AMX_BF16) */
+#define CPUID_1E_1_EAX_AMX_BF16_MIRROR (1U << 1)
+/* AMX_COMPLEX instruction (mirror of CPUID_7_1_EDX_AMX_COMPLEX) */
+#define CPUID_1E_1_EAX_AMX_COMPLEX_MIRROR (1U << 2)
+/* AMX_FP16 instruction (mirror of CPUID_7_1_EAX_AMX_FP16) */
+#define CPUID_1E_1_EAX_AMX_FP16_MIRROR (1U << 3)
+/* AMX_FP8 instruction */
+#define CPUID_1E_1_EAX_AMX_FP8 (1U << 4)
+/* AMX_TF32 instruction */
+#define CPUID_1E_1_EAX_AMX_TF32 (1U << 6)
+/* AMX_AVX512 instruction */
+#define CPUID_1E_1_EAX_AMX_AVX512 (1U << 7)
+/* AMX_MOVRS instruction */
+#define CPUID_1E_1_EAX_AMX_MOVRS (1U << 8)
+
/* AVX10 128-bit vector support is present */
#define CPUID_24_0_EBX_AVX10_128 (1U << 16)
/* AVX10 256-bit vector support is present */
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 03/10] i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration
2025-11-20 7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
2025-11-20 7:10 ` [PATCH 01/10] i386/cpu: Add support for MOVRS in CPUID enumeration Zhao Liu
2025-11-20 7:10 ` [PATCH 02/10] i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions Zhao Liu
@ 2025-11-20 7:10 ` Zhao Liu
2025-11-20 7:10 ` [PATCH 04/10] i386/cpu: Support AVX10.2 with AVX10 feature models Zhao Liu
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-11-20 7:10 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé; +Cc: qemu-devel, Xudong Hao, Zhao Liu
AVX10_VNNI_INT (0x24.0x1.ECX[bit 2]) is a discrete feature bit
introduced on Intel Diamond Rapids, which enumerates the support for
EVEX VPDP* instructions for INT8/INT16 [*].
Although Intel AVX10.2 has already included new VPDP* INT8/INT16 VNNI
instructions, a bit - AVX10_VNNI_INT - is still be separated. Relevant
new instructions can be checked by either CPUID AVX10.2 OR
AVX10_VNNI_INT (e.g., VPDPBSSD).
Support CPUID 0x24.0x1 subleaf with AVX10_VNNI_INT enumeration for
Guest.
[*]: Intel Advanced Vector Extensions 10.2 Architecture Specification
(rev 5.0).
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Reference link: https://cdrdv2.intel.com/v1/dl/getContent/856721
---
target/i386/cpu.c | 29 ++++++++++++++++++++++++++++-
target/i386/cpu.h | 4 ++++
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1985a6b3b835..0a6bb9ec21c5 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1038,6 +1038,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
#define TCG_24_0_EBX_FEATURES 0
#define TCG_29_0_EBX_FEATURES 0
#define TCG_1E_1_EAX_FEATURES 0
+#define TCG_24_1_ECX_FEATURES 0
#if defined CONFIG_USER_ONLY
#define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \
@@ -1385,6 +1386,18 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
},
.tcg_features = TCG_29_0_EBX_FEATURES,
},
+ [FEAT_24_1_ECX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ [2] = "avx10-vnni-int",
+ },
+ .cpuid = {
+ .eax = 0x24,
+ .needs_ecx = true, .ecx = 1,
+ .reg = R_ECX,
+ },
+ .tcg_features = TCG_24_1_ECX_FEATURES,
+ },
[FEAT_8000_0007_EDX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
@@ -2041,6 +2054,11 @@ static FeatureDep feature_dependencies[] = {
.from = { FEAT_7_1_EDX, CPUID_7_1_EDX_APX },
.to = { FEAT_29_0_EBX, ~0ull },
},
+
+ {
+ .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
+ .to = { FEAT_24_1_ECX, ~0ull },
+ },
};
typedef struct X86RegisterInfo32 {
@@ -8457,8 +8475,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ebx = 0;
*ecx = 0;
*edx = 0;
- if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) {
+
+ if (!(env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) {
+ break;
+ }
+ if (count == 0) {
+ uint32_t unused;
+ x86_cpu_get_supported_cpuid(0x1E, 0, eax, &unused,
+ &unused, &unused);
*ebx = env->features[FEAT_24_0_EBX] | env->avx10_version;
+ } else if (count == 1) {
+ *ecx = env->features[FEAT_24_1_ECX];
}
break;
}
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index df57b41567eb..970a4d03a560 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -699,6 +699,7 @@ typedef enum FeatureWord {
FEAT_24_0_EBX, /* CPUID[EAX=0x24,ECX=0].EBX */
FEAT_29_0_EBX, /* CPUID[EAX=0x29,ECX=0].EBX */
FEAT_1E_1_EAX, /* CPUID[EAX=0x1E,ECX=1].EAX */
+ FEAT_24_1_ECX, /* CPUID[EAX=0x24,ECX=0].ECX */
FEATURE_WORDS,
} FeatureWord;
@@ -1100,6 +1101,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
CPUID_24_0_EBX_AVX10_256 | \
CPUID_24_0_EBX_AVX10_512)
+/* AVX10_VNNI_INT instruction */
+#define CPUID_24_1_ECX_AVX10_VNNI_INT (1U << 2)
+
/*
* New Conditional Instructions (NCIs), explicit New Data Destination (NDD)
* controls, and explicit Flags Suppression (NF) controls for select sets of
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 04/10] i386/cpu: Support AVX10.2 with AVX10 feature models
2025-11-20 7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
` (2 preceding siblings ...)
2025-11-20 7:10 ` [PATCH 03/10] i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration Zhao Liu
@ 2025-11-20 7:10 ` Zhao Liu
2025-11-20 7:10 ` [PATCH 05/10] i386/cpu: Add a helper to get host avx10 version Zhao Liu
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-11-20 7:10 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé; +Cc: qemu-devel, Xudong Hao, Zhao Liu
Intel AVX10 Version 2 (Intel AVX10.2) includes a suite of new
instructions delivering new AI features and performance, accelerated
media processing, expanded Web Assembly, and Cryptography support, along
with enhancements to existing legacy instructions for completeness and
efficiency, and it is enumerated as version 2 in CPUID 0x24.0x0.EBX[bits
0-7] [*].
Considerring "Intel CPUs which support Intel AVX10.2 will include an
enumeration for AVX10_VNNI_INT (CPUID.24H.01H:ECX.AVX10_VNNI_INT[2])"
[*] and EVEX VPDP* instructions for INT8/INT16 (AVX10_VNNI_INT) are
detected by either AVX10.2 OR AVX10_VNNI_INT, AVX10_VNNI_INT is part of
AVX10.2, so any Intel AVX10.2 implementation lacking the AVX10_VNNI_INT
enumeration should be considered buggy hardware.
Therefore, it's necessary to set AVX10_VNNI_INT enumeration for Guest
when the user specifies AVX10 version 2. For this, introduce AVX10
models to explicitly define the feature bits included in different AVX10
versions.
[*]: Intel Advanced Vector Extensions 10.2 Architecture Specification
(rev 5.0).
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Reference link: https://cdrdv2.intel.com/v1/dl/getContent/856721
---
target/i386/cpu.c | 120 +++++++++++++++++++++++++++++++++++++++++++---
target/i386/cpu.h | 2 +
2 files changed, 115 insertions(+), 7 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0a6bb9ec21c5..f0ed575dce59 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2382,6 +2382,40 @@ x86_cpu_def_get_versions(const X86CPUDefinition *def)
return def->versions ?: default_version_list;
}
+/* CPUID 0x24.0x0 (EAX, EBX, ECX, EDX) and 0x24.0x1 (EAX, EBX, ECX, EDX) */
+#define AVX10_FEATURE_WORDS 8
+
+typedef struct AVX10VersionDefinition {
+ const char *name;
+ /* AVX10 version */
+ uint8_t version;
+ /* AVX10 (CPUID 0x24) maximum supported sub-leaf. */
+ uint8_t max_subleaf;
+ FeatureMask *features;
+} AVX10VersionDefinition;
+
+static const AVX10VersionDefinition builtin_avx10_defs[] = {
+ {
+ .name = "avx10.1",
+ .version = 1,
+ .max_subleaf = 0,
+ .features = (FeatureMask[]) {
+ { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
+ { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK },
+ { /* end of list */ }
+ }
+ },
+ {
+ .name = "avx10.2",
+ .version = 2,
+ .max_subleaf = 1,
+ .features = (FeatureMask[]) {
+ { FEAT_24_1_ECX, CPUID_24_1_ECX_AVX10_VNNI_INT },
+ { /* end of list */ }
+ }
+ },
+};
+
static const CPUCaches epyc_cache_info = {
.l1d_cache = &(CPUCacheInfo) {
.type = DATA_CACHE,
@@ -7242,6 +7276,65 @@ static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
}
+static void x86_cpuid_get_avx10_version(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
+{
+ X86CPU *cpu = X86_CPU(obj);
+ uint8_t value;
+
+ value = cpu->env.avx10_version;
+ visit_type_uint8(v, name, &value, errp);
+}
+
+static bool x86_cpu_apply_avx10_features(X86CPU *cpu, uint8_t version,
+ Error **errp)
+{
+ const AVX10VersionDefinition *def;
+ CPUX86State *env = &cpu->env;
+
+ if (!version) {
+ env->avx10_version = 0;
+ env->avx10_max_subleaf = 0;
+ return true;
+ }
+
+ for (int i = 0; i < ARRAY_SIZE(builtin_avx10_defs); i++) {
+ FeatureMask *f;
+
+ def = &builtin_avx10_defs[i];
+ for (f = def->features; f && f->mask; f++) {
+ env->features[f->index] |= f->mask;
+ }
+
+ if (def->version == version) {
+ env->avx10_version = version;
+ env->avx10_max_subleaf = def->max_subleaf;
+ break;
+ }
+ }
+
+ if (def->version < version) {
+ error_setg(errp, "avx10-version can be at most %d", def->version);
+ return false;
+ }
+ return true;
+}
+
+static void x86_cpuid_set_avx10_version(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
+{
+ X86CPU *cpu = X86_CPU(obj);
+ uint8_t value;
+
+ if (!visit_type_uint8(v, name, &value, errp)) {
+ return;
+ }
+
+ x86_cpu_apply_avx10_features(cpu, value, errp);
+}
+
/* Generic getter for "feature-words" and "filtered-features" properties */
static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
const char *name, void *opaque,
@@ -7932,8 +8025,10 @@ static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model)
*/
object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
- object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version,
- &error_abort);
+ if (def->avx10_version) {
+ object_property_set_uint(OBJECT(cpu), "avx10-version",
+ def->avx10_version, &error_abort);
+ }
x86_cpu_apply_version_props(cpu, model);
@@ -8480,9 +8575,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
break;
}
if (count == 0) {
- uint32_t unused;
- x86_cpu_get_supported_cpuid(0x1E, 0, eax, &unused,
- &unused, &unused);
+ *eax = env->avx10_max_subleaf;
*ebx = env->features[FEAT_24_0_EBX] | env->avx10_version;
} else if (count == 1) {
*ecx = env->features[FEAT_24_1_ECX];
@@ -9164,7 +9257,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) {
uint32_t eax, ebx, ecx, edx;
x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx);
- env->avx10_version = ebx & 0xff;
+
+ if (!object_property_set_uint(OBJECT(cpu), "avx10-version",
+ ebx & 0xff, errp)) {
+ return;
+ }
}
}
@@ -9393,6 +9490,11 @@ static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose)
warn_report("%s: avx10.%d. Adjust to avx10.%d",
prefix, env->avx10_version, version);
}
+ /*
+ * Discrete feature bits have been checked and filtered based on
+ * host support. So it's safe to change version without reverting
+ * other feature bits.
+ */
env->avx10_version = version;
have_filtered_features = true;
}
@@ -10229,7 +10331,6 @@ static const Property x86_cpu_properties[] = {
DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
- DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0),
DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
@@ -10371,6 +10472,11 @@ static void x86_cpu_common_class_init(ObjectClass *oc, const void *data)
x86_cpu_get_unavailable_features,
NULL, NULL, NULL);
+ object_class_property_add(oc, "avx10-version", "uint8",
+ x86_cpuid_get_avx10_version,
+ x86_cpuid_set_avx10_version,
+ NULL, NULL);
+
#if !defined(CONFIG_USER_ONLY)
object_class_property_add(oc, "crash-information", "GuestPanicInformation",
x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 970a4d03a560..a0b8a59f6c98 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2185,6 +2185,8 @@ typedef struct CPUArchState {
FeatureWordArray features;
/* AVX10 version */
uint8_t avx10_version;
+ /* AVX10 (CPUID 0x24) maximum supported sub-leaf. */
+ uint8_t avx10_max_subleaf;
/* Features that were explicitly enabled/disabled */
FeatureWordArray user_features;
uint32_t cpuid_model[12];
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 05/10] i386/cpu: Add a helper to get host avx10 version
2025-11-20 7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
` (3 preceding siblings ...)
2025-11-20 7:10 ` [PATCH 04/10] i386/cpu: Support AVX10.2 with AVX10 feature models Zhao Liu
@ 2025-11-20 7:10 ` Zhao Liu
2025-11-20 7:10 ` [PATCH 06/10] i386/cpu: Allow cache to be shared at thread level Zhao Liu
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-11-20 7:10 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé; +Cc: qemu-devel, Xudong Hao, Zhao Liu
Factor out a helper to get host avx10 version, to reduce duplicate
codes.
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
target/i386/cpu.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f0ed575dce59..118ce43e4267 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7757,6 +7757,13 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
#endif /* !CONFIG_USER_ONLY */
+static uint8_t x86_cpu_get_host_avx10_version(void)
+{
+ uint32_t eax, ebx, ecx, edx;
+ x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx);
+ return ebx & 0xff;
+}
+
uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w)
{
FeatureWordInfo *wi = &feature_word_info[w];
@@ -9255,11 +9262,10 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
}
if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) {
- uint32_t eax, ebx, ecx, edx;
- x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx);
+ uint8_t version = x86_cpu_get_host_avx10_version();
if (!object_property_set_uint(OBJECT(cpu), "avx10-version",
- ebx & 0xff, errp)) {
+ version, errp)) {
return;
}
}
@@ -9481,9 +9487,7 @@ static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose)
have_filtered_features = x86_cpu_have_filtered_features(cpu);
if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) {
- x86_cpu_get_supported_cpuid(0x24, 0,
- &eax_0, &ebx_0, &ecx_0, &edx_0);
- uint8_t version = ebx_0 & 0xff;
+ uint8_t version = x86_cpu_get_host_avx10_version();
if (version < env->avx10_version) {
if (prefix) {
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 06/10] i386/cpu: Allow cache to be shared at thread level
2025-11-20 7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
` (4 preceding siblings ...)
2025-11-20 7:10 ` [PATCH 05/10] i386/cpu: Add a helper to get host avx10 version Zhao Liu
@ 2025-11-20 7:10 ` Zhao Liu
2025-11-20 7:10 ` [PATCH 07/10] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f Zhao Liu
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-11-20 7:10 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé; +Cc: qemu-devel, Xudong Hao, Zhao Liu
In CPUID 0x4 leaf, it's possible to make the cache privated at thread
level when there's no HT within the core. In this case, while cache per
thread and cache per core are essentially identical, their topology
information differs in CPUID 0x4.
Diamond Rapids assigns the L1 i/d cache at the thread level. To allow
accurate emulation of DMR cache topology, remove the cache-per-thread
restriction in max_thread_ids_for_cache(), which enables CPUID 0x4 to
support cache per thread topology.
Given that after adding thread-level support, the topology offset
information required by max_thread_ids_for_cache() can be sufficiently
provided by apicid_offset_by_topo_level(), so it's straightforward to
re-implement max_thread_ids_for_cache() based on
apicid_offset_by_topo_level() to reduce redundant duplicate codes.
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
target/i386/cpu.c | 53 ++++++++++++++---------------------------------
1 file changed, 15 insertions(+), 38 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 118ce43e4267..c5f1f5d18d07 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -304,33 +304,30 @@ static void encode_cache_cpuid2(X86CPU *cpu,
((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
0 /* Invalid value */)
-static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
- enum CpuTopologyLevel share_level)
+static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
+ enum CpuTopologyLevel topo_level)
{
- uint32_t num_ids = 0;
-
- switch (share_level) {
+ switch (topo_level) {
+ case CPU_TOPOLOGY_LEVEL_THREAD:
+ return 0;
case CPU_TOPOLOGY_LEVEL_CORE:
- num_ids = 1 << apicid_core_offset(topo_info);
- break;
+ return apicid_core_offset(topo_info);
case CPU_TOPOLOGY_LEVEL_MODULE:
- num_ids = 1 << apicid_module_offset(topo_info);
- break;
+ return apicid_module_offset(topo_info);
case CPU_TOPOLOGY_LEVEL_DIE:
- num_ids = 1 << apicid_die_offset(topo_info);
- break;
+ return apicid_die_offset(topo_info);
case CPU_TOPOLOGY_LEVEL_SOCKET:
- num_ids = 1 << apicid_pkg_offset(topo_info);
- break;
+ return apicid_pkg_offset(topo_info);
default:
- /*
- * Currently there is no use case for THREAD, so use
- * assert directly to facilitate debugging.
- */
g_assert_not_reached();
}
+ return 0;
+}
- return num_ids - 1;
+static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
+ enum CpuTopologyLevel share_level)
+{
+ return (1 << apicid_offset_by_topo_level(topo_info, share_level)) - 1;
}
static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info)
@@ -398,26 +395,6 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info,
return 0;
}
-static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
- enum CpuTopologyLevel topo_level)
-{
- switch (topo_level) {
- case CPU_TOPOLOGY_LEVEL_THREAD:
- return 0;
- case CPU_TOPOLOGY_LEVEL_CORE:
- return apicid_core_offset(topo_info);
- case CPU_TOPOLOGY_LEVEL_MODULE:
- return apicid_module_offset(topo_info);
- case CPU_TOPOLOGY_LEVEL_DIE:
- return apicid_die_offset(topo_info);
- case CPU_TOPOLOGY_LEVEL_SOCKET:
- return apicid_pkg_offset(topo_info);
- default:
- g_assert_not_reached();
- }
- return 0;
-}
-
static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level)
{
switch (topo_level) {
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 07/10] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f
2025-11-20 7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
` (5 preceding siblings ...)
2025-11-20 7:10 ` [PATCH 06/10] i386/cpu: Allow cache to be shared at thread level Zhao Liu
@ 2025-11-20 7:10 ` Zhao Liu
2025-11-20 7:10 ` [PATCH 08/10] i386/cpu: Define dependency for VMX_VM_ENTRY_LOAD_IA32_FRED Zhao Liu
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-11-20 7:10 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé; +Cc: qemu-devel, Xudong Hao, Zhao Liu
Many Intel CPUs enable CPUID 0x1f by default to encode CPU topology
information.
Add the "cpuid_0x1f" option to X86CPUDefinition to allow named CPU
models to configure CPUID 0x1f from the start, thereby forcing 0x1f
to be present for guest.
With this option, there's no need to explicitly add v1 model to an
unversioned CPU model for explicitly enabling the x-force-cpuid-0x1f
property.
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Note: this patch is also inclued in Zhaoxin's series:
https://lore.kernel.org/qemu-devel/20251027102139.270662-2-ewanhai-oc@zhaoxin.com/
---
target/i386/cpu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c5f1f5d18d07..143b3e9e0c21 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2313,6 +2313,12 @@ typedef struct X86CPUDefinition {
int model;
int stepping;
uint8_t avx10_version;
+ /*
+ * Whether to present CPUID 0x1f by default.
+ * If true, encode CPU topology in 0x1f leaf even if there's no
+ * extended topology levels.
+ */
+ bool cpuid_0x1f;
FeatureWordArray features;
const char *model_id;
const CPUCaches *const cache_info;
@@ -8014,6 +8020,10 @@ static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model)
def->avx10_version, &error_abort);
}
+ if (def->cpuid_0x1f) {
+ object_property_set_bool(OBJECT(cpu), "x-force-cpuid-0x1f",
+ def->cpuid_0x1f, &error_abort);
+ }
x86_cpu_apply_version_props(cpu, model);
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 08/10] i386/cpu: Define dependency for VMX_VM_ENTRY_LOAD_IA32_FRED
2025-11-20 7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
` (6 preceding siblings ...)
2025-11-20 7:10 ` [PATCH 07/10] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f Zhao Liu
@ 2025-11-20 7:10 ` Zhao Liu
2025-11-20 7:10 ` [PATCH 09/10] i386/cpu: Add CPU model for Diamond Rapids Zhao Liu
2025-11-20 7:10 ` [PATCH 10/10] dosc/cpu-models-x86: Add documentation for DiamondRapids Zhao Liu
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-11-20 7:10 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé; +Cc: qemu-devel, Xudong Hao, Zhao Liu
VMX_VM_ENTRY_LOAD_IA32_FRED depends on FRED. Define this dependency
relationship.
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
target/i386/cpu.c | 4 ++++
target/i386/cpu.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 143b3e9e0c21..e891883fa72f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2036,6 +2036,10 @@ static FeatureDep feature_dependencies[] = {
.from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 },
.to = { FEAT_24_1_ECX, ~0ull },
},
+ {
+ .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED },
+ .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_IA32_FRED },
+ },
};
typedef struct X86RegisterInfo32 {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a0b8a59f6c98..2631bd25981a 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1426,6 +1426,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
#define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
#define VMX_VM_ENTRY_LOAD_CET 0x00100000
#define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
+#define VMX_VM_ENTRY_LOAD_IA32_FRED 0x00800000
/* Supported Hyper-V Enlightenments */
#define HYPERV_FEAT_RELAXED 0
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 09/10] i386/cpu: Add CPU model for Diamond Rapids
2025-11-20 7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
` (7 preceding siblings ...)
2025-11-20 7:10 ` [PATCH 08/10] i386/cpu: Define dependency for VMX_VM_ENTRY_LOAD_IA32_FRED Zhao Liu
@ 2025-11-20 7:10 ` Zhao Liu
2025-11-20 7:10 ` [PATCH 10/10] dosc/cpu-models-x86: Add documentation for DiamondRapids Zhao Liu
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-11-20 7:10 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé; +Cc: qemu-devel, Xudong Hao, Zhao Liu
According to table 1-2 in Intel Architecture Instruction Set Extensions
and Future Features (rev 059), Diamond Rapids has the following new
features which have already been supported for guest:
* SM4 (EVEX)
* Intel Advanced Vector Extensions 10 Version 2 (Intel AVX10.2)
* MOVRS and the PREFETCHRST2 instruction
* AMX-MOVRS, AMX-AVX512, AMX-FP8, AMX-TF32
* Intel Advanced Performance Extensions
And FRED - Flexible Return and Event Delivery (FRED) and the LKGS
instruction (introduced since Clearwater Forest & Diamond Rapids) - is
included in Diamond Rapids CPU model.
In addition, the following features are added into Diamond Rapids CPU
model:
* CET: Control-flow Enforcement Technology (introduced since Sapphire
Rapids & Sierra Forest).
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Reference link: https://cdrdv2.intel.com/v1/dl/getContent/865891
---
target/i386/cpu.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 192 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e891883fa72f..e2d728d38d6f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5443,6 +5443,198 @@ static const X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ },
},
},
+ {
+ .name = "DiamondRapids",
+ .level = 0x29,
+ .vendor = CPUID_VENDOR_INTEL,
+ .family = 0x13, /* family: 0xf, extended famil: 0x4 */
+ .model = 0x1, /* model: 0x1, extended model: 0x0 */
+ .stepping = 0,
+ .avx10_version = 2, /* avx10.2 */
+ .cpuid_0x1f = true,
+ /*
+ * Please keep the ascending order so that we can have a clear view of
+ * bit position of each feature.
+ *
+ * Missing: CPUID_EXT_DTES64, CPUID_EXT_MONITOR, CPUID_EXT_DSCPL,
+ * CPUID_EXT_VMX, CPUID_EXT_SMX, CPUID_EXT_EST, CPUID_EXT_TM2,
+ * CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_DCA, CPUID_EXT_OSXSAVE
+ */
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
+ CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
+ CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
+ CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
+ CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+ /* Missing: CPUID_DTS, CPUID_ACPI, CPUID_HT, CPUID_TM, CPUID_PBE */
+ .features[FEAT_1_EDX] =
+ CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
+ CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+ CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
+ CPUID_SSE | CPUID_SSE2 | CPUID_SS,
+ .features[FEAT_6_EAX] = CPUID_6_EAX_ARAT,
+ /*
+ * Missing: CPUID_7_0_EBX_SGX, "cqm" Cache QoS Monitoring,
+ * "rdt_a" Resource Director Technology Allocation,
+ * CPUID_7_0_EBX_INTEL_PT,
+ */
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST |
+ CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 |
+ CPUID_7_0_EBX_FDP_EXCPTN_ONLY | CPUID_7_0_EBX_SMEP |
+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
+ CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_ZERO_FCS_FDS |
+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
+ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
+ CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
+ CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD |
+ CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_AVX512BW |
+ CPUID_7_0_EBX_AVX512VL,
+ /*
+ * Missing: CPUID_7_0_ECX_OSPKE, CPUID_7_0_ECX_WAITPKG, TME, ENQCMD,
+ * CPUID_7_0_ECX_SGX_LC, CPUID_7_0_ECX_PKS
+ */
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP |
+ CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_AVX512_VBMI2 |
+ CPUID_7_0_ECX_CET_SHSTK | CPUID_7_0_ECX_GFNI | CPUID_7_0_ECX_VAES |
+ CPUID_7_0_ECX_VPCLMULQDQ | CPUID_7_0_ECX_AVX512VNNI |
+ CPUID_7_0_ECX_AVX512BITALG | CPUID_7_0_ECX_AVX512_VPOPCNTDQ |
+ CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_RDPID |
+ CPUID_7_0_ECX_BUS_LOCK_DETECT | CPUID_7_0_ECX_CLDEMOTE |
+ CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_MOVDIR64B,
+ /*
+ * Missing: SGX-KEYS, UINTR, PCONFIG, ARCH LBR,
+ * CPUID_7_0_EDX_CORE_CAPABILITY
+ */
+ .features[FEAT_7_0_EDX] =
+ CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_MD_CLEAR |
+ CPUID_7_0_EDX_SERIALIZE | CPUID_7_0_EDX_TSX_LDTRK |
+ CPUID_7_0_EDX_CET_IBT | CPUID_7_0_EDX_AMX_BF16 |
+ CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
+ CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
+ CPUID_7_0_EDX_STIBP | CPUID_7_0_EDX_FLUSH_L1D |
+ CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
+ /* Missing: CPUID_7_1_EAX_LASS, ArchPerfmonExt (0x23 leaf), MSRLIST */
+ .features[FEAT_7_1_EAX] =
+ CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
+ CPUID_7_1_EAX_CMPCCXADD | CPUID_7_1_EAX_FZRM |
+ CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_FRED |
+ CPUID_7_1_EAX_LKGS | CPUID_7_1_EAX_WRMSRNS |
+ CPUID_7_1_EAX_AMX_FP16 | CPUID_7_1_EAX_AVX_IFMA |
+ CPUID_7_1_EAX_LAM | CPUID_7_1_EAX_MOVRS,
+ /* Missing: CET_SSS */
+ .features[FEAT_7_1_EDX] =
+ CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT |
+ CPUID_7_1_EDX_AMX_COMPLEX | CPUID_7_1_EDX_PREFETCHITI |
+ CPUID_7_1_EDX_AVX10 | CPUID_7_1_EDX_APX,
+ /* Missing: UC-lock disable */
+ .features[FEAT_7_2_EDX] =
+ CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL |
+ CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U |
+ CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO,
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+ CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
+ .features[FEAT_1E_1_EAX] =
+ CPUID_1E_1_EAX_AMX_INT8_MIRROR | CPUID_1E_1_EAX_AMX_BF16_MIRROR |
+ CPUID_1E_1_EAX_AMX_COMPLEX_MIRROR |
+ CPUID_1E_1_EAX_AMX_FP16_MIRROR | CPUID_1E_1_EAX_AMX_FP8 |
+ CPUID_1E_1_EAX_AMX_TF32 | CPUID_1E_1_EAX_AMX_AVX512 |
+ CPUID_1E_1_EAX_AMX_MOVRS,
+ .features[FEAT_29_0_EBX] = CPUID_29_0_EBX_APX_NCI_NDD_NF,
+ /*
+ * Though this bit will be set by avx_version=2, it's better to
+ * explicitly enumerate this feature here.
+ */
+ .features[FEAT_24_1_ECX] = CPUID_24_1_ECX_AVX10_VNNI_INT,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
+ CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
+ .features[FEAT_8000_0008_EBX] = CPUID_8000_0008_EBX_WBNOINVD,
+ /*
+ * Missing: ARCH_CAP_RRSBA (KVM bit 19), ARCH_CAP_RFDS_CLEAR (KVM bit
+ * 28), MCU_CONTROL (bit 9), MISC_PACKAGE_CTLS (bit 10),
+ * ENERGY_FILTERING_CTL (bit 11), DOITM (bit 12), MCU_ENUMERATION (bit
+ * 16), RRSBA (bit 19), XAPIC_DISABLE_STATUS (bit 21),
+ * OVERCLOCKING_STATUS (bit 23).
+ */
+ .features[FEAT_ARCH_CAPABILITIES] =
+ MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
+ MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
+ MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO |
+ MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO |
+ MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_BHI_NO |
+ MSR_ARCH_CAP_PBRSB_NO | MSR_ARCH_CAP_GDS_NO |
+ MSR_ARCH_CAP_RFDS_NO,
+ .features[FEAT_VMX_BASIC] =
+ MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS |
+ MSR_VMX_BASIC_NESTED_EXCEPTION,
+ .features[FEAT_VMX_ENTRY_CTLS] =
+ VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
+ VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
+ VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER |
+ VMX_VM_ENTRY_LOAD_CET | VMX_VM_ENTRY_LOAD_IA32_FRED,
+ .features[FEAT_VMX_EPT_VPID_CAPS] =
+ MSR_VMX_EPT_EXECONLY |
+ MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
+ MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
+ MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
+ MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
+ MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
+ MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
+ MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
+ .features[FEAT_VMX_EXIT_CTLS] =
+ VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE,
+ VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
+ VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
+ VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
+ VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER |
+ VMX_VM_EXIT_SAVE_CET | VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS,
+ .features[FEAT_VMX_MISC] =
+ MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
+ MSR_VMX_MISC_ACTIVITY_SHUTDOWN | MSR_VMX_MISC_ACTIVITY_WAIT_SIPI |
+ MSR_VMX_MISC_VMWRITE_VMEXIT,
+ .features[FEAT_VMX_PINBASED_CTLS] =
+ VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
+ VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
+ VMX_PIN_BASED_POSTED_INTR,
+ .features[FEAT_VMX_PROCBASED_CTLS] =
+ VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
+ VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
+ VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
+ VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
+ VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
+ VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
+ VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
+ VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
+ VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
+ VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
+ VMX_CPU_BASED_PAUSE_EXITING |
+ VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
+ .features[FEAT_VMX_SECONDARY_CTLS] =
+ VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+ VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
+ VMX_SECONDARY_EXEC_RDTSCP |
+ VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
+ VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
+ VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
+ VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
+ VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+ VMX_SECONDARY_EXEC_RDRAND_EXITING |
+ VMX_SECONDARY_EXEC_ENABLE_INVPCID |
+ VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
+ VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
+ VMX_SECONDARY_EXEC_XSAVES | VMX_SECONDARY_EXEC_TSC_SCALING |
+ VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE,
+ .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
+ .xlevel = 0x80000008,
+ .model_id = "Intel Xeon Processor (DiamondRapids)",
+ },
{
.name = "SierraForest",
.level = 0x23,
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 10/10] dosc/cpu-models-x86: Add documentation for DiamondRapids
2025-11-20 7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
` (8 preceding siblings ...)
2025-11-20 7:10 ` [PATCH 09/10] i386/cpu: Add CPU model for Diamond Rapids Zhao Liu
@ 2025-11-20 7:10 ` Zhao Liu
9 siblings, 0 replies; 11+ messages in thread
From: Zhao Liu @ 2025-11-20 7:10 UTC (permalink / raw)
To: Paolo Bonzini, Daniel P . Berrangé
Cc: qemu-devel, Xudong Hao, Zhao Liu, Yu Chen
Current DiamondRapids hasn't supported cache model. Instead, document
its special CPU & cache topology to allow user emulate with "-smp" &
"-machine smp-cache".
Cc: Yu Chen <yu.c.chen@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
docs/system/cpu-models-x86.rst.inc | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc
index 6a770ca8351c..c4c8fc67a562 100644
--- a/docs/system/cpu-models-x86.rst.inc
+++ b/docs/system/cpu-models-x86.rst.inc
@@ -71,6 +71,26 @@ mixture of host CPU models between machines, if live migration
compatibility is required, use the newest CPU model that is compatible
across all desired hosts.
+``DiamondRapids``
+ Intel Xeon Processor.
+
+ Diamond Rapids product has a topology which differs from previous Xeon
+ products. It does not support SMT, but instead features a dual core
+ module (DCM) architecture. It also has core building blocks (CBB - die
+ level in CPU topology). The cache hierarchy is organized as follows:
+ L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per
+ CBB. This cache topology can be emulated for DiamondRapids CPU model
+ using the smp-cache configuration as shown below:
+
+ Example:
+
+ ::
+
+ -machine smp-cache.0.cache=l1d,smp-cache.0.topology=thread,\
+ smp-cache.1.cache=l1i,smp-cache.1.topology=thread,\
+ smp-cache.2.cache=l2,smp-cache.2.topology=module,\
+ smp-cache.3.cache=l3,smp-cache.3.topology=die\
+
``ClearwaterForest``
Intel Xeon Processor (ClearwaterForest, 2025)
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread