From: Zhao Liu <zhao1.liu@intel.com>
To: "Paolo Bonzini" <pbonzini@redhat.com>,
"Daniel P . Berrangé" <berrange@redhat.com>
Cc: qemu-devel@nongnu.org, Xudong Hao <xudong.hao@intel.com>,
Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH 07/10] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f
Date: Thu, 20 Nov 2025 15:10:27 +0800 [thread overview]
Message-ID: <20251120071030.961230-8-zhao1.liu@intel.com> (raw)
In-Reply-To: <20251120071030.961230-1-zhao1.liu@intel.com>
Many Intel CPUs enable CPUID 0x1f by default to encode CPU topology
information.
Add the "cpuid_0x1f" option to X86CPUDefinition to allow named CPU
models to configure CPUID 0x1f from the start, thereby forcing 0x1f
to be present for guest.
With this option, there's no need to explicitly add v1 model to an
unversioned CPU model for explicitly enabling the x-force-cpuid-0x1f
property.
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Note: this patch is also inclued in Zhaoxin's series:
https://lore.kernel.org/qemu-devel/20251027102139.270662-2-ewanhai-oc@zhaoxin.com/
---
target/i386/cpu.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c5f1f5d18d07..143b3e9e0c21 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2313,6 +2313,12 @@ typedef struct X86CPUDefinition {
int model;
int stepping;
uint8_t avx10_version;
+ /*
+ * Whether to present CPUID 0x1f by default.
+ * If true, encode CPU topology in 0x1f leaf even if there's no
+ * extended topology levels.
+ */
+ bool cpuid_0x1f;
FeatureWordArray features;
const char *model_id;
const CPUCaches *const cache_info;
@@ -8014,6 +8020,10 @@ static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model)
def->avx10_version, &error_abort);
}
+ if (def->cpuid_0x1f) {
+ object_property_set_bool(OBJECT(cpu), "x-force-cpuid-0x1f",
+ def->cpuid_0x1f, &error_abort);
+ }
x86_cpu_apply_version_props(cpu, model);
/*
--
2.34.1
next prev parent reply other threads:[~2025-11-20 6:49 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-20 7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
2025-11-20 7:10 ` [PATCH 01/10] i386/cpu: Add support for MOVRS in CPUID enumeration Zhao Liu
2025-11-20 7:10 ` [PATCH 02/10] i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions Zhao Liu
2025-11-20 7:10 ` [PATCH 03/10] i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration Zhao Liu
2025-11-20 7:10 ` [PATCH 04/10] i386/cpu: Support AVX10.2 with AVX10 feature models Zhao Liu
2025-11-20 7:10 ` [PATCH 05/10] i386/cpu: Add a helper to get host avx10 version Zhao Liu
2025-11-20 7:10 ` [PATCH 06/10] i386/cpu: Allow cache to be shared at thread level Zhao Liu
2025-11-20 7:10 ` Zhao Liu [this message]
2025-11-20 7:10 ` [PATCH 08/10] i386/cpu: Define dependency for VMX_VM_ENTRY_LOAD_IA32_FRED Zhao Liu
2025-11-20 7:10 ` [PATCH 09/10] i386/cpu: Add CPU model for Diamond Rapids Zhao Liu
2025-11-20 7:10 ` [PATCH 10/10] dosc/cpu-models-x86: Add documentation for DiamondRapids Zhao Liu
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