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From: Zhao Liu <zhao1.liu@intel.com>
To: "Paolo Bonzini" <pbonzini@redhat.com>,
	"Daniel P . Berrangé" <berrange@redhat.com>
Cc: qemu-devel@nongnu.org, Xudong Hao <xudong.hao@intel.com>,
	Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH 08/10] i386/cpu: Define dependency for VMX_VM_ENTRY_LOAD_IA32_FRED
Date: Thu, 20 Nov 2025 15:10:28 +0800	[thread overview]
Message-ID: <20251120071030.961230-9-zhao1.liu@intel.com> (raw)
In-Reply-To: <20251120071030.961230-1-zhao1.liu@intel.com>

VMX_VM_ENTRY_LOAD_IA32_FRED depends on FRED. Define this dependency
relationship.

Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
 target/i386/cpu.c | 4 ++++
 target/i386/cpu.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 143b3e9e0c21..e891883fa72f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2036,6 +2036,10 @@ static FeatureDep feature_dependencies[] = {
         .from = { FEAT_7_1_EDX,             CPUID_7_1_EDX_AVX10 },
         .to = { FEAT_24_1_ECX,              ~0ull },
     },
+    {
+        .from = { FEAT_7_1_EAX,             CPUID_7_1_EAX_FRED },
+        .to = { FEAT_VMX_ENTRY_CTLS,        VMX_VM_ENTRY_LOAD_IA32_FRED },
+    },
 };
 
 typedef struct X86RegisterInfo32 {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a0b8a59f6c98..2631bd25981a 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1426,6 +1426,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL             0x00040000
 #define VMX_VM_ENTRY_LOAD_CET                       0x00100000
 #define VMX_VM_ENTRY_LOAD_IA32_PKRS                 0x00400000
+#define VMX_VM_ENTRY_LOAD_IA32_FRED                 0x00800000
 
 /* Supported Hyper-V Enlightenments */
 #define HYPERV_FEAT_RELAXED             0
-- 
2.34.1



  parent reply	other threads:[~2025-11-20  6:50 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-20  7:10 [PATCH 00/10] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids Zhao Liu
2025-11-20  7:10 ` [PATCH 01/10] i386/cpu: Add support for MOVRS in CPUID enumeration Zhao Liu
2025-11-20  7:10 ` [PATCH 02/10] i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions Zhao Liu
2025-11-20  7:10 ` [PATCH 03/10] i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration Zhao Liu
2025-11-20  7:10 ` [PATCH 04/10] i386/cpu: Support AVX10.2 with AVX10 feature models Zhao Liu
2025-11-20  7:10 ` [PATCH 05/10] i386/cpu: Add a helper to get host avx10 version Zhao Liu
2025-11-20  7:10 ` [PATCH 06/10] i386/cpu: Allow cache to be shared at thread level Zhao Liu
2025-11-20  7:10 ` [PATCH 07/10] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f Zhao Liu
2025-11-20  7:10 ` Zhao Liu [this message]
2025-11-20  7:10 ` [PATCH 09/10] i386/cpu: Add CPU model for Diamond Rapids Zhao Liu
2025-11-20  7:10 ` [PATCH 10/10] dosc/cpu-models-x86: Add documentation for DiamondRapids Zhao Liu

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