[RFC-PATCH-for-11.0 v2 0/8] accel/tcg: Remove some MO_TE uses in cpu_ld{uw, l, q}_code()

[RFC-PATCH-for-11.0 v2 0/8] accel/tcg: Remove some MO_TE uses in cpu_ld{uw, l, q}_code()

[Philippe Mathieu-Daudé]

Quick attempt to remove MO_TE uses for fixed-endianness targets.

v2: convert all but mips targets and remove unexplicit API.

Philippe Mathieu-Daudé (8):
  accel/tcg: Add endianness variants of cpu_ld{uw,l,q}_code()
  target/alpha: Use little-endian variant of cpu_ldl_code()
  target/loongarch: Use little-endian variant of cpu_ldl_code()
  target/sparc: Use big-endian variant of cpu_ldl_code()
  target/s390x: Use big-endian variant of cpu_ld{uw,l}_code()
  target/riscv: Use little-endian variant of cpu_ld{l,q}_code()
  target/ppc: Replace cpu_ldl_code() by explicit endianness variants
  accel/tcg: Remove non-explicit endian cpu_ld*_code() helpers

 include/accel/tcg/cpu-ldst.h   | 33 +++++++++++++++++++++++++++------
 target/alpha/mem_helper.c      |  2 +-
 target/loongarch/tcg/tcg_cpu.c |  2 +-
 target/ppc/tcg-excp_helper.c   | 17 +++--------------
 target/riscv/translate.c       |  2 +-
 target/riscv/zce_helper.c      |  4 ++--
 target/s390x/tcg/mem_helper.c  |  6 +++---
 target/sparc/int32_helper.c    |  2 +-
 8 files changed, 39 insertions(+), 29 deletions(-)

-- 
2.51.0

[RFC-PATCH-for-11.0 v2 1/8] accel/tcg: Add endianness variants of cpu_ld{uw, l, q}_code()

[Philippe Mathieu-Daudé]

Allow target with fixed-endianness to not use the MO_TE definition.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/accel/tcg/cpu-ldst.h | 43 +++++++++++++++++++++++++++++++-----
 1 file changed, 37 insertions(+), 6 deletions(-)

diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h
index 0de7f5eaa6b..e4ec4e7d367 100644
--- a/include/accel/tcg/cpu-ldst.h
+++ b/include/accel/tcg/cpu-ldst.h
@@ -481,25 +481,56 @@ static inline uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
     return cpu_ldb_code_mmu(env, addr, oi, 0);
 }
 
-static inline uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
+static inline uint32_t cpu_lduw_le_code(CPUArchState *env, abi_ptr addr)
 {
     CPUState *cs = env_cpu(env);
-    MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(cs, true));
+    MemOpIdx oi = make_memop_idx(MO_LEUW, cpu_mmu_index(cs, true));
     return cpu_ldw_code_mmu(env, addr, oi, 0);
 }
 
-static inline uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
+static inline uint32_t cpu_ldl_le_code(CPUArchState *env, abi_ptr addr)
 {
     CPUState *cs = env_cpu(env);
-    MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(cs, true));
+    MemOpIdx oi = make_memop_idx(MO_LEUL, cpu_mmu_index(cs, true));
     return cpu_ldl_code_mmu(env, addr, oi, 0);
 }
 
-static inline uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
+static inline uint64_t cpu_ldq_le_code(CPUArchState *env, abi_ptr addr)
 {
     CPUState *cs = env_cpu(env);
-    MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(cs, true));
+    MemOpIdx oi = make_memop_idx(MO_LEUQ, cpu_mmu_index(cs, true));
     return cpu_ldq_code_mmu(env, addr, oi, 0);
 }
 
+static inline uint32_t cpu_lduw_be_code(CPUArchState *env, abi_ptr addr)
+{
+    CPUState *cs = env_cpu(env);
+    MemOpIdx oi = make_memop_idx(MO_BEUW, cpu_mmu_index(cs, true));
+    return cpu_ldw_code_mmu(env, addr, oi, 0);
+}
+
+static inline uint32_t cpu_ldl_be_code(CPUArchState *env, abi_ptr addr)
+{
+    CPUState *cs = env_cpu(env);
+    MemOpIdx oi = make_memop_idx(MO_BEUL, cpu_mmu_index(cs, true));
+    return cpu_ldl_code_mmu(env, addr, oi, 0);
+}
+
+static inline uint64_t cpu_ldq_be_code(CPUArchState *env, abi_ptr addr)
+{
+    CPUState *cs = env_cpu(env);
+    MemOpIdx oi = make_memop_idx(MO_BEUQ, cpu_mmu_index(cs, true));
+    return cpu_ldq_code_mmu(env, addr, oi, 0);
+}
+
+#if TARGET_BIG_ENDIAN
+# define cpu_lduw_code        cpu_lduw_be_code
+# define cpu_ldl_code         cpu_ldl_be_code
+# define cpu_ldq_code         cpu_ldq_be_code
+#else
+# define cpu_lduw_code        cpu_lduw_le_code
+# define cpu_ldl_code         cpu_ldl_le_code
+# define cpu_ldq_code         cpu_ldq_le_code
+#endif
+
 #endif /* ACCEL_TCG_CPU_LDST_H */
-- 
2.51.0

[RFC-PATCH-for-11.0 v2 2/8] target/alpha: Use little-endian variant of cpu_ldl_code()

[Philippe Mathieu-Daudé]

Alpha instructions are always stored in little-endian order.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/alpha/mem_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c
index 2113fe33ae2..d04d086b59d 100644
--- a/target/alpha/mem_helper.c
+++ b/target/alpha/mem_helper.c
@@ -30,7 +30,7 @@ static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t retadd
     cpu_restore_state(env_cpu(env), retaddr);
 
     pc = env->pc;
-    insn = cpu_ldl_code(env, pc);
+    insn = cpu_ldl_le_code(env, pc);
 
     env->trap_arg0 = addr;
     env->trap_arg1 = insn >> 26;                /* opcode */
-- 
2.51.0

[RFC-PATCH-for-11.0 v2 3/8] target/loongarch: Use little-endian variant of cpu_ldl_code()

[Philippe Mathieu-Daudé]

LoongArch instructions are always stored in little-endian order.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/loongarch/tcg/tcg_cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c
index 9d077c56d9d..3f4b5f9258e 100644
--- a/target/loongarch/tcg/tcg_cpu.c
+++ b/target/loongarch/tcg/tcg_cpu.c
@@ -140,7 +140,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
     }
 
     if (update_badinstr) {
-        env->CSR_BADI = cpu_ldl_code(env, env->pc);
+        env->CSR_BADI = cpu_ldl_le_code(env, env->pc);
     }
 
     /* Save PLV and IE */
-- 
2.51.0

[RFC-PATCH-for-11.0 v2 4/8] target/sparc: Use big-endian variant of cpu_ldl_code()

[Philippe Mathieu-Daudé]

SPARC instructions are always stored in big-endian order.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sparc/int32_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c
index b29f693a6bf..a777d17a01c 100644
--- a/target/sparc/int32_helper.c
+++ b/target/sparc/int32_helper.c
@@ -151,7 +151,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
         if (!env->fsr_qne) {
             env->fsr_qne = FSR_QNE;
             env->fq.s.addr = env->pc;
-            env->fq.s.insn = cpu_ldl_code(env, env->pc);
+            env->fq.s.insn = cpu_ldl_be_code(env, env->pc);
         }
         env->pc = env->npc;
         env->npc = env->npc + 4;
-- 
2.51.0

[RFC-PATCH-for-11.0 v2 5/8] target/s390x: Use big-endian variant of cpu_ld{uw, l}_code()

[Philippe Mathieu-Daudé]

S390x instructions are always stored in big-endian order.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/s390x/tcg/mem_helper.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 24675fc818d..84d901c2008 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -2437,7 +2437,7 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr)
         tcg_s390_program_interrupt(env, PGM_SPECIFICATION, GETPC());
     }
 
-    insn = cpu_lduw_code(env, addr);
+    insn = cpu_lduw_be_code(env, addr);
     opc = insn >> 8;
 
     /* Or in the contents of R1[56:63].  */
@@ -2449,10 +2449,10 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr)
     case 2:
         break;
     case 4:
-        insn |= (uint64_t)cpu_lduw_code(env, addr + 2) << 32;
+        insn |= (uint64_t)cpu_lduw_be_code(env, addr + 2) << 32;
         break;
     case 6:
-        insn |= (uint64_t)(uint32_t)cpu_ldl_code(env, addr + 2) << 16;
+        insn |= (uint64_t)(uint32_t)cpu_ldl_be_code(env, addr + 2) << 16;
         break;
     default:
         g_assert_not_reached();
-- 
2.51.0

[RFC-PATCH-for-11.0 v2 6/8] target/riscv: Use little-endian variant of cpu_ld{l, q}_code()

[Philippe Mathieu-Daudé]

RISC-V instructions are always stored in little-endian order
(see "Volume I: RISC-V Unprivileged ISA" document, chapter
'Instruction Encoding Spaces and Prefixes': "instruction fetch
in RISC-V is little-endian").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/translate.c  | 2 +-
 target/riscv/zce_helper.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e1f4dc5ffd0..847481a9b41 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1182,7 +1182,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
     CPUState *cpu = ctx->cs;
     CPURISCVState *env = cpu_env(cpu);
 
-    return cpu_ldl_code(env, pc);
+    return cpu_ldl_le_code(env, pc);
 }
 
 #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE)
diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c
index 55221f5f375..992e2f964e0 100644
--- a/target/riscv/zce_helper.c
+++ b/target/riscv/zce_helper.c
@@ -44,10 +44,10 @@ target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index)
 
     if (xlen == 32) {
         t0 = base + (index << 2);
-        target = cpu_ldl_code(env, t0);
+        target = cpu_ldl_le_code(env, t0);
     } else {
         t0 = base + (index << 3);
-        target = cpu_ldq_code(env, t0);
+        target = cpu_ldq_le_code(env, t0);
     }
 
     return target & ~0x1;
-- 
2.51.0

[RFC-PATCH-for-11.0 v2 7/8] target/ppc: Replace cpu_ldl_code() by explicit endianness variants

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/tcg-excp_helper.c | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c
index edecfb85725..6058efb09cd 100644
--- a/target/ppc/tcg-excp_helper.c
+++ b/target/ppc/tcg-excp_helper.c
@@ -424,22 +424,11 @@ G_NORETURN void powerpc_checkstop(CPUPPCState *env, const char *reason)
     cpu_loop_exit_noexc(cs);
 }
 
-/* Return true iff byteswap is needed to load instruction */
-static inline bool insn_need_byteswap(CPUArchState *env)
-{
-    /* SYSTEM builds TARGET_BIG_ENDIAN. Need to swap when MSR[LE] is set */
-    return !!(env->msr & ((target_ulong)1 << MSR_LE));
-}
-
 uint32_t ppc_ldl_code(CPUArchState *env, target_ulong addr)
 {
-    uint32_t insn = cpu_ldl_code(env, addr);
-
-    if (insn_need_byteswap(env)) {
-        insn = bswap32(insn);
-    }
-
-    return insn;
+    return FIELD_EX64(env->msr, MSR, MSR_LE)
+           ? cpu_ldl_le_code(env, addr)
+           : cpu_ldl_be_code(env, addr);
 }
 
 #if defined(TARGET_PPC64)
-- 
2.51.0

[RFC-PATCH-for-11.0 v2 8/8] accel/tcg: Remove non-explicit endian cpu_ld*_code() helpers

[Philippe Mathieu-Daudé]

All uses were converted to the explicit cpu_ld*_{be,le}_code()
helpers, no need for the non-explicit versions anymore.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/accel/tcg/cpu-ldst.h | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h
index e4ec4e7d367..a3125fc9026 100644
--- a/include/accel/tcg/cpu-ldst.h
+++ b/include/accel/tcg/cpu-ldst.h
@@ -523,14 +523,4 @@ static inline uint64_t cpu_ldq_be_code(CPUArchState *env, abi_ptr addr)
     return cpu_ldq_code_mmu(env, addr, oi, 0);
 }
 
-#if TARGET_BIG_ENDIAN
-# define cpu_lduw_code        cpu_lduw_be_code
-# define cpu_ldl_code         cpu_ldl_be_code
-# define cpu_ldq_code         cpu_ldq_be_code
-#else
-# define cpu_lduw_code        cpu_lduw_le_code
-# define cpu_ldl_code         cpu_ldl_le_code
-# define cpu_ldq_code         cpu_ldq_le_code
-#endif
-
 #endif /* ACCEL_TCG_CPU_LDST_H */
-- 
2.51.0