[PATCH v1 1/1] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug

[PATCH v1 1/1] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug

[Jamin Lin via]

This patch updates the ASPEED PCIe Root Port capability layout and interrupt
handling to match the hardware-defined capability structure as documented in
the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet.

The following capability offsets and fields are now aligned with the actual
hardware implementation (validated using EVB config-space dumps via
'lspci -s <bdf> -vvv'):

- Added MSI capability at offset 0x50 and enabled 1-vector MSI support
- Added PCI Express Capability structure at offset 0x80
- Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0
- Added AER capability at offset 0x100
- Implemented aer_vector() callback and MSI init/uninit hooks
- Updated Root Port SSID to 0x1150 to reflect the platform default

Enabling MSI is required for proper PCIe Hotplug event signaling. This change
improves correctness and ensures QEMU Root Port behavior matches the behavior
of ASPEED hardware and downstream kernel expectations.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 39 insertions(+), 1 deletion(-)

diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
index f7593444fc..1fc2c61772 100644
--- a/hw/pci-host/aspeed_pcie.c
+++ b/hw/pci-host/aspeed_pcie.c
@@ -68,6 +68,38 @@ static const TypeInfo aspeed_pcie_root_device_info = {
  * PCIe Root Port
  */
 
+#define ASPEED_PCIE_ROOT_PORT_MSI_OFFSET        0x50
+#define ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR     1
+#define ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET      0xC0
+#define ASPEED_PCIE_ROOT_PORT_EXP_OFFSET        0x80
+#define ASPEED_PCIE_ROOT_PORT_AER_OFFSET        0x100
+
+static uint8_t aspeed_pcie_root_port_aer_vector(const PCIDevice *d)
+{
+    return 0;
+}
+
+static int aspeed_pcie_root_port_interrupts_init(PCIDevice *d, Error **errp)
+{
+    int rc;
+
+    rc = msi_init(d, ASPEED_PCIE_ROOT_PORT_MSI_OFFSET,
+                  ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR,
+                  PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_64BIT,
+                  PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_MASKBIT,
+                  errp);
+    if (rc < 0) {
+        assert(rc == -ENOTSUP);
+    }
+
+    return rc;
+}
+
+static void aspeed_pcie_root_port_interrupts_uninit(PCIDevice *d)
+{
+    msi_uninit(d);
+}
+
 static void aspeed_pcie_root_port_class_init(ObjectClass *klass,
                                              const void *data)
 {
@@ -80,7 +112,13 @@ static void aspeed_pcie_root_port_class_init(ObjectClass *klass,
     k->device_id = 0x1150;
     dc->user_creatable = true;
 
-    rpc->aer_offset = 0x100;
+    rpc->aer_vector = aspeed_pcie_root_port_aer_vector;
+    rpc->interrupts_init = aspeed_pcie_root_port_interrupts_init;
+    rpc->interrupts_uninit = aspeed_pcie_root_port_interrupts_uninit;
+    rpc->exp_offset = ASPEED_PCIE_ROOT_PORT_EXP_OFFSET;
+    rpc->aer_offset = ASPEED_PCIE_ROOT_PORT_AER_OFFSET;
+    rpc->ssvid_offset = ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET;
+    rpc->ssid = 0x1150;
 }
 
 static const TypeInfo aspeed_pcie_root_port_info = {
-- 
2.43.0

[PATCH v1 0/1] (RESEND) Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug

[Jamin Lin via]

v1:
  1.  Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug

How to test it:

Firmware Requirements
 
Before testing, please make sure the Linux kernel has the following configuration enabled:
Reference defconfig:
https://github.com/AspeedTech-BMC/linux/blob/aspeed-master-v6.6/arch/arm64/configs/aspeed_g7_defconfig

CONFIG_HOTPLUG_PCI_PCIE=y
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set

QEMU Testing Procedure
1. Boot Linux and verify the root port

root@ast2700-a1-spl:~# lspci
0002:00:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge

2. Add an e1000e device dynamically (Hot-plug)

In QEMU monitor:
(qemu) device_add e1000e,bus=pcie.2,id=mye1000e
[  103.919703] pcieport 0002:00:00.0: pciehp: Slot(0): Button press: will power on in 5 sec
[  103.921921] pcieport 0002:00:00.0: pciehp: Slot(0): Card present
[  103.922557] pcieport 0002:00:00.0: pciehp: Slot(0): Link Up
[  105.047374] pci 0002:01:00.0: [8086:10d3] type 00 class 0x020000
[  105.048859] pci 0002:01:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[  105.049786] pci 0002:01:00.0: reg 0x14: [mem 0x00000000-0x0001ffff]
[  105.050453] pci 0002:01:00.0: reg 0x18: [io  0x0000-0x001f]
[  105.051049] pci 0002:01:00.0: reg 0x1c: [mem 0x00000000-0x00003fff]
[  105.051904] pci 0002:01:00.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
[  105.052880] pci 0002:01:00.0: enabling Extended Tags
[  105.063878] pci 0002:01:00.0: BAR 6: assigned [mem 0xa0000000-0xa003ffff pref]
[  105.064889] pci 0002:01:00.0: BAR 0: assigned [mem 0xa0040000-0xa005ffff]
[  105.066104] pci 0002:01:00.0: BAR 1: assigned [mem 0xa0060000-0xa007ffff]
[  105.066881] pci 0002:01:00.0: BAR 3: assigned [mem 0xa0080000-0xa0083fff]
[  105.067637] pci 0002:01:00.0: BAR 2: assigned [io  0x1000-0x101f]
[  105.068360] pcieport 0002:00:00.0: PCI bridge to [bus 01]
[  105.068828] pcieport 0002:00:00.0:   bridge window [io  0x1000-0x1fff]
[  105.072140] pcieport 0002:00:00.0:   bridge window [mem 0xa0000000-0xa01fffff]
[  105.075017] pcieport 0002:00:00.0:   bridge window [mem 0xa0200000-0xa03fffff 64bit pref]
[  105.081561] pcieport 0002:00:00.0: Max Payload Size set to  128/ 128 (was  128), Max Read Rq  128
[  105.082733] pci 0002:01:00.0: Max Payload Size set to  128/ 128 (was  128), Max Read Rq  128
[  105.089597] e1000e 0002:01:00.0: enabling device (0000 -> 0002)
[  105.098995] e1000e 0002:01:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode
[  105.160515] e1000e 0002:01:00.0 0002:01:00.0 (uninitialized): registered PHC clock
[  105.231396] e1000e 0002:01:00.0 eth2: (PCI Express:2.5GT/s:Width x1) 52:54:00:12:34:56
[  105.232279] e1000e 0002:01:00.0 eth2: Intel(R) PRO/1000 Network Connection
[  105.233696] e1000e 0002:01:00.0 eth2: MAC: 3, PHY: 8, PBA No: 000000-000
[  105.489627] 8021q: adding VLAN 0 to HW filter on device eth2
[  105.788193] e1000e 0002:01:00.0 eth2: NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx

Leave QEMU monitor mode and lspci now lists the device:

root@ast2700-a1-spl:~# lspci
0002:00:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
0002:01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection

3. Remove the device dynamically (Hot-unplug)  

In QEMU monitor:
(qemu) device_del mye1000e
[  203.354941] pcieport 0002:00:00.0: pciehp: Slot(0): Button press: will power off in 5 sec
[  208.411558] e1000e 0002:01:00.0 eth2: removed PHC
[  208.486799] e1000e 0002:01:00.0 eth2: NIC Link is Down

Leave QEMU monitor mode and lspci again shows only the root port:
root@ast2700-a1-spl:~# lspci
0002:00:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge

Jamin Lin (1):
  hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and
    enable MSI to support hotplug

 hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 39 insertions(+), 1 deletion(-)

-- 
2.43.0

[PATCH v1 1/1] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug

[Jamin Lin via]

This patch updates the ASPEED PCIe Root Port capability layout and interrupt
handling to match the hardware-defined capability structure as documented in
the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet.

The following capability offsets and fields are now aligned with the actual
hardware implementation (validated using EVB config-space dumps via
'lspci -s <bdf> -vvv'):

- Added MSI capability at offset 0x50 and enabled 1-vector MSI support
- Added PCI Express Capability structure at offset 0x80
- Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0
- Added AER capability at offset 0x100
- Implemented aer_vector() callback and MSI init/uninit hooks
- Updated Root Port SSID to 0x1150 to reflect the platform default

Enabling MSI is required for proper PCIe Hotplug event signaling. This change
improves correctness and ensures QEMU Root Port behavior matches the behavior
of ASPEED hardware and downstream kernel expectations.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 39 insertions(+), 1 deletion(-)

diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
index f7593444fc..1fc2c61772 100644
--- a/hw/pci-host/aspeed_pcie.c
+++ b/hw/pci-host/aspeed_pcie.c
@@ -68,6 +68,38 @@ static const TypeInfo aspeed_pcie_root_device_info = {
  * PCIe Root Port
  */
 
+#define ASPEED_PCIE_ROOT_PORT_MSI_OFFSET        0x50
+#define ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR     1
+#define ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET      0xC0
+#define ASPEED_PCIE_ROOT_PORT_EXP_OFFSET        0x80
+#define ASPEED_PCIE_ROOT_PORT_AER_OFFSET        0x100
+
+static uint8_t aspeed_pcie_root_port_aer_vector(const PCIDevice *d)
+{
+    return 0;
+}
+
+static int aspeed_pcie_root_port_interrupts_init(PCIDevice *d, Error **errp)
+{
+    int rc;
+
+    rc = msi_init(d, ASPEED_PCIE_ROOT_PORT_MSI_OFFSET,
+                  ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR,
+                  PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_64BIT,
+                  PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_MASKBIT,
+                  errp);
+    if (rc < 0) {
+        assert(rc == -ENOTSUP);
+    }
+
+    return rc;
+}
+
+static void aspeed_pcie_root_port_interrupts_uninit(PCIDevice *d)
+{
+    msi_uninit(d);
+}
+
 static void aspeed_pcie_root_port_class_init(ObjectClass *klass,
                                              const void *data)
 {
@@ -80,7 +112,13 @@ static void aspeed_pcie_root_port_class_init(ObjectClass *klass,
     k->device_id = 0x1150;
     dc->user_creatable = true;
 
-    rpc->aer_offset = 0x100;
+    rpc->aer_vector = aspeed_pcie_root_port_aer_vector;
+    rpc->interrupts_init = aspeed_pcie_root_port_interrupts_init;
+    rpc->interrupts_uninit = aspeed_pcie_root_port_interrupts_uninit;
+    rpc->exp_offset = ASPEED_PCIE_ROOT_PORT_EXP_OFFSET;
+    rpc->aer_offset = ASPEED_PCIE_ROOT_PORT_AER_OFFSET;
+    rpc->ssvid_offset = ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET;
+    rpc->ssid = 0x1150;
 }
 
 static const TypeInfo aspeed_pcie_root_port_info = {
-- 
2.43.0

Re: [PATCH v1 1/1] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug

[Philippe Mathieu-Daudé]

On 21/11/25 06:01, Jamin Lin via wrote:
> This patch updates the ASPEED PCIe Root Port capability layout and interrupt
> handling to match the hardware-defined capability structure as documented in
> the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet.
> 
> The following capability offsets and fields are now aligned with the actual
> hardware implementation (validated using EVB config-space dumps via
> 'lspci -s <bdf> -vvv'):
> 
> - Added MSI capability at offset 0x50 and enabled 1-vector MSI support
> - Added PCI Express Capability structure at offset 0x80
> - Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0
> - Added AER capability at offset 0x100
> - Implemented aer_vector() callback and MSI init/uninit hooks
> - Updated Root Port SSID to 0x1150 to reflect the platform default
> 
> Enabling MSI is required for proper PCIe Hotplug event signaling. This change
> improves correctness and ensures QEMU Root Port behavior matches the behavior
> of ASPEED hardware and downstream kernel expectations.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 39 insertions(+), 1 deletion(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH v1 1/1] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug

[Nabih Estefan]

On Thu, Nov 20, 2025 at 11:06 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> On 21/11/25 06:01, Jamin Lin via wrote:

Thank you for the quick turnaround on the bug fix, Jamin! Tested it
against internal models
on our end. Hotplugged devices now appear with `lspci`.

> > This patch updates the ASPEED PCIe Root Port capability layout and interrupt
> > handling to match the hardware-defined capability structure as documented in
> > the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet.
> >
> > The following capability offsets and fields are now aligned with the actual
> > hardware implementation (validated using EVB config-space dumps via
> > 'lspci -s <bdf> -vvv'):
> >
> > - Added MSI capability at offset 0x50 and enabled 1-vector MSI support
> > - Added PCI Express Capability structure at offset 0x80
> > - Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0
> > - Added AER capability at offset 0x100
> > - Implemented aer_vector() callback and MSI init/uninit hooks
> > - Updated Root Port SSID to 0x1150 to reflect the platform default
> >
> > Enabling MSI is required for proper PCIe Hotplug event signaling. This change
> > improves correctness and ensures QEMU Root Port behavior matches the behavior
> > of ASPEED hardware and downstream kernel expectations.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++-
> >   1 file changed, 39 insertions(+), 1 deletion(-)
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>
Reviewed-by: Nabih Estefan <nabihestefan@google.com>
Tested-by: Nabih Estefan <nabihestefan@google.com>

Re: [SPAM] [PATCH v1 1/1] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug

[Cédric Le Goater]

On 11/21/25 06:01, Jamin Lin wrote:
> This patch updates the ASPEED PCIe Root Port capability layout and interrupt
> handling to match the hardware-defined capability structure as documented in
> the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet.
> 
> The following capability offsets and fields are now aligned with the actual
> hardware implementation (validated using EVB config-space dumps via
> 'lspci -s <bdf> -vvv'):
> 
> - Added MSI capability at offset 0x50 and enabled 1-vector MSI support
> - Added PCI Express Capability structure at offset 0x80
> - Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0
> - Added AER capability at offset 0x100
> - Implemented aer_vector() callback and MSI init/uninit hooks
> - Updated Root Port SSID to 0x1150 to reflect the platform default
> 
> Enabling MSI is required for proper PCIe Hotplug event signaling. This change
> improves correctness and ensures QEMU Root Port behavior matches the behavior
> of ASPEED hardware and downstream kernel expectations.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 39 insertions(+), 1 deletion(-)


It seems that we should queue this patch for QEMU 10.2. If so,
could you provide a fixes tag please ?

Thanks,

C.


> 
> diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
> index f7593444fc..1fc2c61772 100644
> --- a/hw/pci-host/aspeed_pcie.c
> +++ b/hw/pci-host/aspeed_pcie.c
> @@ -68,6 +68,38 @@ static const TypeInfo aspeed_pcie_root_device_info = {
>    * PCIe Root Port
>    */
>   
> +#define ASPEED_PCIE_ROOT_PORT_MSI_OFFSET        0x50
> +#define ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR     1
> +#define ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET      0xC0
> +#define ASPEED_PCIE_ROOT_PORT_EXP_OFFSET        0x80
> +#define ASPEED_PCIE_ROOT_PORT_AER_OFFSET        0x100
> +
> +static uint8_t aspeed_pcie_root_port_aer_vector(const PCIDevice *d)
> +{
> +    return 0;
> +}
> +
> +static int aspeed_pcie_root_port_interrupts_init(PCIDevice *d, Error **errp)
> +{
> +    int rc;
> +
> +    rc = msi_init(d, ASPEED_PCIE_ROOT_PORT_MSI_OFFSET,
> +                  ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR,
> +                  PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_64BIT,
> +                  PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_MASKBIT,
> +                  errp);
> +    if (rc < 0) {
> +        assert(rc == -ENOTSUP);
> +    }
> +
> +    return rc;
> +}
> +
> +static void aspeed_pcie_root_port_interrupts_uninit(PCIDevice *d)
> +{
> +    msi_uninit(d);
> +}
> +
>   static void aspeed_pcie_root_port_class_init(ObjectClass *klass,
>                                                const void *data)
>   {
> @@ -80,7 +112,13 @@ static void aspeed_pcie_root_port_class_init(ObjectClass *klass,
>       k->device_id = 0x1150;
>       dc->user_creatable = true;
>   
> -    rpc->aer_offset = 0x100;
> +    rpc->aer_vector = aspeed_pcie_root_port_aer_vector;
> +    rpc->interrupts_init = aspeed_pcie_root_port_interrupts_init;
> +    rpc->interrupts_uninit = aspeed_pcie_root_port_interrupts_uninit;
> +    rpc->exp_offset = ASPEED_PCIE_ROOT_PORT_EXP_OFFSET;
> +    rpc->aer_offset = ASPEED_PCIE_ROOT_PORT_AER_OFFSET;
> +    rpc->ssvid_offset = ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET;
> +    rpc->ssid = 0x1150;
>   }
>   
>   static const TypeInfo aspeed_pcie_root_port_info = {

Re: [SPAM] [PATCH v1 1/1] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug

[Cédric Le Goater]

On 11/21/25 06:01, Jamin Lin wrote:
> This patch updates the ASPEED PCIe Root Port capability layout and interrupt
> handling to match the hardware-defined capability structure as documented in
> the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet.
> 
> The following capability offsets and fields are now aligned with the actual
> hardware implementation (validated using EVB config-space dumps via
> 'lspci -s <bdf> -vvv'):
> 
> - Added MSI capability at offset 0x50 and enabled 1-vector MSI support
> - Added PCI Express Capability structure at offset 0x80
> - Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0
> - Added AER capability at offset 0x100
> - Implemented aer_vector() callback and MSI init/uninit hooks
> - Updated Root Port SSID to 0x1150 to reflect the platform default
> 
> Enabling MSI is required for proper PCIe Hotplug event signaling. This change
> improves correctness and ensures QEMU Root Port behavior matches the behavior
> of ASPEED hardware and downstream kernel expectations.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Fixes: 2af56518fa91 ("hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable")


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.


> ---
>   hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 39 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c
> index f7593444fc..1fc2c61772 100644
> --- a/hw/pci-host/aspeed_pcie.c
> +++ b/hw/pci-host/aspeed_pcie.c
> @@ -68,6 +68,38 @@ static const TypeInfo aspeed_pcie_root_device_info = {
>    * PCIe Root Port
>    */
>   
> +#define ASPEED_PCIE_ROOT_PORT_MSI_OFFSET        0x50
> +#define ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR     1
> +#define ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET      0xC0
> +#define ASPEED_PCIE_ROOT_PORT_EXP_OFFSET        0x80
> +#define ASPEED_PCIE_ROOT_PORT_AER_OFFSET        0x100
> +
> +static uint8_t aspeed_pcie_root_port_aer_vector(const PCIDevice *d)
> +{
> +    return 0;
> +}
> +
> +static int aspeed_pcie_root_port_interrupts_init(PCIDevice *d, Error **errp)
> +{
> +    int rc;
> +
> +    rc = msi_init(d, ASPEED_PCIE_ROOT_PORT_MSI_OFFSET,
> +                  ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR,
> +                  PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_64BIT,
> +                  PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_MASKBIT,
> +                  errp);
> +    if (rc < 0) {
> +        assert(rc == -ENOTSUP);
> +    }
> +
> +    return rc;
> +}
> +
> +static void aspeed_pcie_root_port_interrupts_uninit(PCIDevice *d)
> +{
> +    msi_uninit(d);
> +}
> +
>   static void aspeed_pcie_root_port_class_init(ObjectClass *klass,
>                                                const void *data)
>   {
> @@ -80,7 +112,13 @@ static void aspeed_pcie_root_port_class_init(ObjectClass *klass,
>       k->device_id = 0x1150;
>       dc->user_creatable = true;
>   
> -    rpc->aer_offset = 0x100;
> +    rpc->aer_vector = aspeed_pcie_root_port_aer_vector;
> +    rpc->interrupts_init = aspeed_pcie_root_port_interrupts_init;
> +    rpc->interrupts_uninit = aspeed_pcie_root_port_interrupts_uninit;
> +    rpc->exp_offset = ASPEED_PCIE_ROOT_PORT_EXP_OFFSET;
> +    rpc->aer_offset = ASPEED_PCIE_ROOT_PORT_AER_OFFSET;
> +    rpc->ssvid_offset = ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET;
> +    rpc->ssid = 0x1150;
>   }
>   
>   static const TypeInfo aspeed_pcie_root_port_info = {