From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Fabiano Rosas" <farosas@suse.de>,
qemu-block@nongnu.org, "Klaus Jensen" <its@irrelevant.dk>,
"Gustavo Romero" <gustavo.romero@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Keith Busch" <kbusch@kernel.org>,
"Jesper Devantier" <foss@defmacro.it>,
"Laurent Vivier" <lvivier@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH-for-10.2] hw/nvme/ctrl: Validate PMR memory size
Date: Mon, 24 Nov 2025 05:02:01 +0100 [thread overview]
Message-ID: <20251124040201.55117-1-philmd@linaro.org> (raw)
Per the PCI spec 3.0, in section 6.2.5.1, "Address Maps":
A 32-bit register can be implemented to support a single
memory size that is a power of 2 from 16 bytes to 2 GB.
Add a check in nvme_init_pmr(), returning an error if the
PMR region size is too small; and update the QTest.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/nvme/ctrl.c | 13 +++++++++++--
tests/qtest/nvme-test.c | 2 +-
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 4d150c7206a..1df5e88dbbb 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -8819,10 +8819,15 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
}
}
-static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
+static bool nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
{
uint32_t pmrcap = ldl_le_p(&n->bar.pmrcap);
+ if (memory_region_size(&n->pmr.dev->mr) < 16) {
+ error_setg(errp, "PMR device must have at least 16 bytes");
+ return false;
+ }
+
NVME_PMRCAP_SET_RDS(pmrcap, 1);
NVME_PMRCAP_SET_WDS(pmrcap, 1);
NVME_PMRCAP_SET_BIR(pmrcap, NVME_PMR_BIR);
@@ -8837,6 +8842,8 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmr.dev->mr);
memory_region_set_enabled(&n->pmr.dev->mr, false);
+
+ return true;
}
static uint64_t nvme_mbar_size(unsigned total_queues, unsigned total_irqs,
@@ -9055,7 +9062,9 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
}
if (n->pmr.dev) {
- nvme_init_pmr(n, pci_dev);
+ if (!nvme_init_pmr(n, pci_dev, errp)) {
+ return false;
+ }
}
return true;
diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c
index 5ad6821f7af..4aec1651e6e 100644
--- a/tests/qtest/nvme-test.c
+++ b/tests/qtest/nvme-test.c
@@ -149,7 +149,7 @@ static void nvme_register_nodes(void)
.before_cmd_line = "-drive id=drv0,if=none,file=null-co://,"
"file.read-zeroes=on,format=raw "
"-object memory-backend-ram,id=pmr0,"
- "share=on,size=8",
+ "share=on,size=16",
};
add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) });
--
2.51.0
next reply other threads:[~2025-11-24 4:02 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-24 4:02 Philippe Mathieu-Daudé [this message]
2025-11-24 10:45 ` [PATCH-for-10.2] hw/nvme/ctrl: Validate PMR memory size Klaus Jensen
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