From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Jason Wang" <jasowang@redhat.com>,
"Gustavo Romero" <gustavo.romero@linaro.org>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH] hw/pci: Use correct bus aperture for device container size
Date: Mon, 24 Nov 2025 12:47:54 +0100 [thread overview]
Message-ID: <20251124114754.79831-1-philmd@linaro.org> (raw)
Before commit 3716d5902d7 ("pci: introduce a bus master container")
device view of the bus address space was correctly sized to the
bus aperture, but then it always used a 64-bit aperture. Restore
the previous behavior, so devices on 32-bit PCI only see 32-bit
address space.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/pci/pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index b1eba348e06..64f33b9de04 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1375,7 +1375,8 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
- "bus master container", UINT64_MAX);
+ "bus master container",
+ memory_region_size(bus->address_space_mem));
address_space_init(&pci_dev->bus_master_as,
&pci_dev->bus_master_container_region, pci_dev->name);
pci_dev->bus_master_as.max_bounce_buffer_size =
--
2.51.0
next reply other threads:[~2025-11-24 11:48 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-24 11:47 Philippe Mathieu-Daudé [this message]
2025-11-25 15:45 ` [PATCH] hw/pci: Use correct bus aperture for device container size Yodel Eldar via
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