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Tue, 25 Nov 2025 03:47:47 -0500 (EST) From: Klaus Jensen To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Klaus Jensen , Keith Busch , Klaus Jensen , Jesper Devantier , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , qemu-block@nongnu.org Subject: [PULL 3/3] hw/nvme: Validate PMR memory size Date: Tue, 25 Nov 2025 09:47:25 +0100 Message-ID: <20251125084725.4632-4-its@irrelevant.dk> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251125084725.4632-1-its@irrelevant.dk> References: <20251125084725.4632-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=202.12.124.156; envelope-from=its@irrelevant.dk; helo=fhigh-b5-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé Per the PCI spec 3.0, in section 6.2.5.1, "Address Maps": A 32-bit register can be implemented to support a single memory size that is a power of 2 from 16 bytes to 2 GB. Add a check in nvme_init_pmr(), returning an error if the PMR region size is too small; and update the QTest. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Klaus Jensen Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 13 +++++++++++-- tests/qtest/nvme-test.c | 2 +- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 901d4d863355..cc4593cd427a 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8814,10 +8814,15 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) } } -static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev) +static bool nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) { uint32_t pmrcap = ldl_le_p(&n->bar.pmrcap); + if (memory_region_size(&n->pmr.dev->mr) < 16) { + error_setg(errp, "PMR device must have at least 16 bytes"); + return false; + } + NVME_PMRCAP_SET_RDS(pmrcap, 1); NVME_PMRCAP_SET_WDS(pmrcap, 1); NVME_PMRCAP_SET_BIR(pmrcap, NVME_PMR_BIR); @@ -8832,6 +8837,8 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev) PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmr.dev->mr); memory_region_set_enabled(&n->pmr.dev->mr, false); + + return true; } static uint64_t nvme_mbar_size(unsigned total_queues, unsigned total_irqs, @@ -9050,7 +9057,9 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) } if (n->pmr.dev) { - nvme_init_pmr(n, pci_dev); + if (!nvme_init_pmr(n, pci_dev, errp)) { + return false; + } } return true; diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c index 5ad6821f7af9..4aec1651e6e2 100644 --- a/tests/qtest/nvme-test.c +++ b/tests/qtest/nvme-test.c @@ -149,7 +149,7 @@ static void nvme_register_nodes(void) .before_cmd_line = "-drive id=drv0,if=none,file=null-co://," "file.read-zeroes=on,format=raw " "-object memory-backend-ram,id=pmr0," - "share=on,size=8", + "share=on,size=16", }; add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) }); -- 2.51.0