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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7fa35b7sm39542842f8f.20.2025.11.25.23.50.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Nov 2025 23:50:33 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH-for-11.0 v2 04/12] target/riscv: Use little-endian variant of cpu_ld/st_data*() for vector Date: Wed, 26 Nov 2025 08:49:55 +0100 Message-ID: <20251126075003.4826-5-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251126075003.4826-1-philmd@linaro.org> References: <20251126075003.4826-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org RISC-V vector "elements are simply packed in order from the least-signicant to most-signicant bits of the vector register" [*] which is little endianness, therefore the cpu_ld/st_data*() definitions expand to the little endian declarations. Use the explicit little-endian variants. [*] RISC-V "V" Vector Extension v1.0 Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/vector_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2de3358ee86..caa8dd9c125 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -193,9 +193,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host) \ } GEN_VEXT_LD_ELEM(lde_b, uint8_t, H1, ldub) -GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw) -GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl) -GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq) +GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw_le) +GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl_le) +GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq_le) #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ static inline QEMU_ALWAYS_INLINE \ @@ -214,9 +214,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host) \ } GEN_VEXT_ST_ELEM(ste_b, uint8_t, H1, stb) -GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw) -GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl) -GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq) +GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw_le) +GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl_le) +GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq_le) static inline QEMU_ALWAYS_INLINE void vext_continuous_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb, -- 2.51.0