From: Jim MacArthur <jim.macarthur@linaro.org>
To: qemu-devel@nongnu.org
Cc: Jim MacArthur <jim.macarthur@linaro.org>
Subject: [PATCH V3 3/4] target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max
Date: Wed, 26 Nov 2025 12:36:49 +0000 [thread overview]
Message-ID: <20251126124116.351685-4-jim.macarthur@linaro.org> (raw)
In-Reply-To: <20251126124116.351685-1-jim.macarthur@linaro.org>
Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
target/arm/tcg/cpu64.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 6871956382..ef4c0c8d73 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1334,6 +1334,10 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* FEAT_AIE */
SET_IDREG(isar, ID_AA64MMFR3, t);
+ t = GET_IDREG(isar, ID_AA64MMFR4);
+ t = FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* FEAT_ASID2 */
+ SET_IDREG(isar, ID_AA64MMFR4, t);
+
t = GET_IDREG(isar, ID_AA64ZFR0);
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */
t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
--
2.43.0
next prev parent reply other threads:[~2025-11-26 12:42 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-26 12:36 [PATCH V3 0/4] Basic ASID2 Support Jim MacArthur
2025-11-26 12:36 ` [PATCH V3 1/4] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur
2025-11-26 12:36 ` [PATCH V3 2/4] target/arm: Allow writes to FNG1, FNG0, A2 Jim MacArthur
2025-11-26 12:36 ` Jim MacArthur [this message]
2025-11-26 12:36 ` [PATCH V3 4/4] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur
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