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([2a10:d582:31e:0:a692:d4e2:eaed:fc4e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7f2e556sm40044246f8f.5.2025.11.26.04.41.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 04:41:21 -0800 (PST) From: Jim MacArthur To: qemu-devel@nongnu.org Cc: Jim MacArthur Subject: [PATCH V3 4/4] tests: Add test for ASID2 and write/read of feature bits Date: Wed, 26 Nov 2025 12:36:50 +0000 Message-ID: <20251126124116.351685-5-jim.macarthur@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251126124116.351685-1-jim.macarthur@linaro.org> References: <20251126124116.351685-1-jim.macarthur@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=jim.macarthur@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Test for presence of ASID2; if it is, check FNG1, FNG0, and A2 are writable, and read value shows the update. If not present, check these read as RES0. Signed-off-by: Jim MacArthur --- tests/tcg/aarch64/system/asid2.c | 75 ++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 tests/tcg/aarch64/system/asid2.c diff --git a/tests/tcg/aarch64/system/asid2.c b/tests/tcg/aarch64/system/asid2.c new file mode 100644 index 0000000000..a4887e4ce2 --- /dev/null +++ b/tests/tcg/aarch64/system/asid2.c @@ -0,0 +1,75 @@ +/* + * ASID2 Feature presence and enabled TCR2_EL1 bits test + * + * Copyright (c) 2025 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +#define ID_AA64MMFR3_EL1 "S3_0_C0_C7_3" +#define ID_AA64MMFR4_EL1 "S3_0_C0_C7_4" +#define TCR2_EL1 "S3_0_C2_C0_3" + +int main() +{ + /* + * Test for presence of ASID2 and three feature bits enabled by it: + * https://developer.arm.com/documentation/109697/2025_09/Feature-descriptions/The-Armv9-5-architecture-extension + * Bits added are FNG1, FNG0, and A2. These should be RES0 if A2 is + * not enabled and read as the written value if A2 is enabled. + */ + + uint64_t out; + uint64_t idreg3; + uint64_t idreg4; + int tcr2_present; + int asid2_present; + + /* Mask is FNG1, FNG0, and A2 */ + const uint64_t feature_mask = (1ULL << 18 | 1ULL << 17 | 1ULL << 16); + const uint64_t in = feature_mask; + + asm("mrs %[x1], " ID_AA64MMFR3_EL1 "\n\t" + : [x1] "=r" (idreg3)); + + tcr2_present = ((idreg3 & 0xF) != 0); + + if (!tcr2_present) { + ml_printf("TCR2 is not present, cannot perform test"); + return 0; + } + + asm("mrs %[x1], " ID_AA64MMFR4_EL1 "\n\t" + : [x1] "=r" (idreg4)); + + asid2_present = ((idreg4 & 0xF00) != 0); + + asm("msr " TCR2_EL1 ", %[x0]\n\t" + "mrs %[x1], " TCR2_EL1 "\n\t" + : [x1] "=r" (out) + : [x0] "r" (in)); + + if (asid2_present) { + if ((out & feature_mask) == in) { + ml_printf("OK\n"); + return 0; + } else { + ml_printf("FAIL: ASID2 present, but read value %lx != " + "written value %lx\n", + out & feature_mask, in); + return 1; + } + } else { + if (out == 0) { + ml_printf("TCR2_EL1 reads as RES0 as expected\n"); + return 0; + } else { + ml_printf("FAIL: ASID2, missing but read value %lx != 0\n", + out & feature_mask, in); + return 1; + } + } +} -- 2.43.0