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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7fd8e54sm44005646f8f.40.2025.11.26.12.24.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 26 Nov 2025 12:24:30 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Nicholas Piggin , Chinmay Rath Subject: [PATCH-for-11.0 v3 21/22] target/ppc: Simplify endianness handling in Altivec opcodes Date: Wed, 26 Nov 2025 21:21:57 +0100 Message-ID: <20251126202200.23100-22-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251126202200.23100-1-philmd@linaro.org> References: <20251126202200.23100-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Access the memory in big-endian order, swap bytes when MSR.LE is set. Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/mem_helper.c | 31 ++++++++++--------------------- 1 file changed, 10 insertions(+), 21 deletions(-) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index cff385b6020..cfc67a527c1 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -31,15 +31,6 @@ /* #define DEBUG_OP */ -static inline bool needs_byteswap(const CPUPPCState *env) -{ -#if TARGET_BIG_ENDIAN - return FIELD_EX64(env->msr, MSR, LE); -#else - return !FIELD_EX64(env->msr, MSR, LE); -#endif -} - /*****************************************************************************/ /* Memory load and stores */ @@ -421,11 +412,10 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, int adjust = HI_IDX * (n_elems - 1); \ int sh = sizeof(r->element[0]) >> 1; \ int index = (addr & 0xf) >> sh; \ - if (FIELD_EX64(env->msr, MSR, LE)) { \ - index = n_elems - index - 1; \ - } \ + bool byteswap = FIELD_EX64(env->msr, MSR, LE); \ \ - if (needs_byteswap(env)) { \ + if (byteswap) { \ + index = n_elems - index - 1; \ r->element[LO_IDX ? index : (adjust - index)] = \ swap(access(env, addr, GETPC())); \ } else { \ @@ -435,8 +425,8 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, } #define I(x) (x) LVE(LVEBX, cpu_ldub_data_ra, I, u8) -LVE(LVEHX, cpu_lduw_data_ra, bswap16, u16) -LVE(LVEWX, cpu_ldl_data_ra, bswap32, u32) +LVE(LVEHX, cpu_lduw_be_data_ra, bswap16, u16) +LVE(LVEWX, cpu_ldl_be_data_ra, bswap32, u32) #undef I #undef LVE @@ -448,11 +438,10 @@ LVE(LVEWX, cpu_ldl_data_ra, bswap32, u32) int adjust = HI_IDX * (n_elems - 1); \ int sh = sizeof(r->element[0]) >> 1; \ int index = (addr & 0xf) >> sh; \ - if (FIELD_EX64(env->msr, MSR, LE)) { \ - index = n_elems - index - 1; \ - } \ + bool byteswap = FIELD_EX64(env->msr, MSR, LE); \ \ - if (needs_byteswap(env)) { \ + if (byteswap) { \ + index = n_elems - index - 1; \ access(env, addr, swap(r->element[LO_IDX ? index : \ (adjust - index)]), \ GETPC()); \ @@ -463,8 +452,8 @@ LVE(LVEWX, cpu_ldl_data_ra, bswap32, u32) } #define I(x) (x) STVE(STVEBX, cpu_stb_data_ra, I, u8) -STVE(STVEHX, cpu_stw_data_ra, bswap16, u16) -STVE(STVEWX, cpu_stl_data_ra, bswap32, u32) +STVE(STVEHX, cpu_stw_be_data_ra, bswap16, u16) +STVE(STVEWX, cpu_stl_be_data_ra, bswap32, u32) #undef I #undef LVE -- 2.51.0