* [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data()
@ 2025-11-26 20:21 Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 01/22] target/hexagon: Use little-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé
` (21 more replies)
0 siblings, 22 replies; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé
Since v2:
- Reworked SH4
- Completed PPC / MIPS.
Since v1:
- Fixed s/little/big/ typo (thuth)
Still trying to remove MO_TE uses, here looking at cpu_ld/st_data()
in fixed-endianness targets.
Series split of bigger one [*] where Richard made a comment on
*_code() patches. Since not related to *_data() uses, post separetely
since almost ready (still few PPC/MIPS paths to update, but I'd rather
check if this is heading in the correct direction before looking at
them).
[*] https://lore.kernel.org/qemu-devel/20251121134503.30914-1-philmd@linaro.org/
Philippe Mathieu-Daudé (22):
target/hexagon: Use little-endian variant of cpu_ld/st_data*()
target/i386: Use little-endian variant of cpu_ld/st_data*()
target/riscv: Use little-endian variant of cpu_ld/st_data*() for
vector
target/rx: Use little-endian variant of cpu_ld/st_data*()
target/tricore: Use little-endian variant of cpu_ld/st_data*()
target/hppa: Use big-endian variant of cpu_ld/st_data*()
target/m68k: Use big-endian variant of cpu_ld/st_data*()
target/s390x: Use big-endian variant of cpu_ld/st_data*()
target/sparc: Use big-endian variant of cpu_ld/st_data*()
target/sh4: Replace cpu_stl_data() call in OCBI helper
target/mips: Use big-endian variant of cpu_ld/st_data*() for MSA
opcode
target/mips: Introduce loadu8() & loads4() helpers
target/mips: Pass MemOpIdx to atomic load helpers
target/mips: Drop almask argument of HELPER_LD_ATOMIC() macro
target/mips: Inline cpu_ld*_mmuidx_ra() calls in atomic load helpers
target/mips: Expand HELPER_LD_ATOMIC()
target/mips: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers
target/ppc: Inline cpu_ld/st_data_ra() calls in do_hash()
target/ppc: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers
target/ppc: Inline cpu_ldl_data_ra() calls in ICBI helper
target/ppc: Simplify endianness handling in Altivec opcodes
accel/tcg: Remove non-explicit endian cpu_ld/st*_data*() helpers
include/accel/tcg/cpu-ldst.h | 46 --------
target/hexagon/macros.h | 6 +-
target/i386/ops_sse.h | 12 +--
target/i386/tcg/seg_helper.h | 12 +--
linux-user/vm86.c | 4 +-
target/hexagon/op_helper.c | 6 +-
target/hppa/op_helper.c | 44 ++++----
target/i386/tcg/mem_helper.c | 8 +-
target/i386/tcg/mpx_helper.c | 28 ++---
target/i386/tcg/seg_helper.c | 16 +--
target/i386/tcg/system/excp_helper.c | 8 +-
target/i386/tcg/system/svm_helper.c | 69 ++++++------
target/m68k/fpu_helper.c | 12 +--
target/m68k/op_helper.c | 91 ++++++++--------
target/mips/tcg/ldst_helper.c | 108 ++++++++++++-------
target/mips/tcg/msa_helper.c | 51 +++++----
target/mips/tcg/translate.c | 9 +-
target/ppc/mem_helper.c | 75 +++++++------
target/ppc/tcg-excp_helper.c | 9 +-
target/riscv/vector_helper.c | 12 +--
target/rx/helper.c | 14 +--
target/rx/op_helper.c | 6 +-
target/s390x/tcg/mem_helper.c | 48 ++++-----
target/s390x/tcg/vec_helper.c | 8 +-
target/sh4/op_helper.c | 5 +-
target/sparc/ldst_helper.c | 6 +-
target/tricore/op_helper.c | 152 +++++++++++++--------------
27 files changed, 440 insertions(+), 425 deletions(-)
--
2.51.0
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 01/22] target/hexagon: Use little-endian variant of cpu_ld/st_data*()
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 02/22] target/i386: " Philippe Mathieu-Daudé
` (20 subsequent siblings)
21 siblings, 0 replies; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Brian Cain
We only build the Hexagon target using little endianness order,
therefore the cpu_ld/st_data*() definitions expand to the little
endian declarations. Use the explicit little-endian variants.
Mechanical change running:
$ tgt=hexagon; \
end=le; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/macros.h | 6 +++---
target/hexagon/op_helper.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 088e5961ab7..6c2862a2320 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -519,9 +519,9 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
#define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
#else
#define MEM_LOAD1 cpu_ldub_data_ra
-#define MEM_LOAD2 cpu_lduw_data_ra
-#define MEM_LOAD4 cpu_ldl_data_ra
-#define MEM_LOAD8 cpu_ldq_data_ra
+#define MEM_LOAD2 cpu_lduw_le_data_ra
+#define MEM_LOAD4 cpu_ldl_le_data_ra
+#define MEM_LOAD8 cpu_ldq_le_data_ra
#define fLOAD(NUM, SIZE, SIGN, EA, DST) \
do { \
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index e2e80ca7efa..08db1e9c56b 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -77,13 +77,13 @@ static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra)
cpu_stb_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra);
break;
case 2:
- cpu_stw_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra);
+ cpu_stw_le_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra);
break;
case 4:
- cpu_stl_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra);
+ cpu_stl_le_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra);
break;
case 8:
- cpu_stq_data_ra(env, va, env->mem_log_stores[slot_num].data64, ra);
+ cpu_stq_le_data_ra(env, va, env->mem_log_stores[slot_num].data64, ra);
break;
default:
g_assert_not_reached();
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 02/22] target/i386: Use little-endian variant of cpu_ld/st_data*()
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 01/22] target/hexagon: Use little-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 03/22] target/riscv: Use little-endian variant of cpu_ld/st_data*() for vector Philippe Mathieu-Daudé
` (19 subsequent siblings)
21 siblings, 0 replies; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Laurent Vivier, Paolo Bonzini,
Zhao Liu, Eduardo Habkost
We only build the X86 targets using little endianness order,
therefore the cpu_ld/st_data*() definitions expand to the little
endian declarations. Use the explicit little-endian variants.
Mechanical change running:
$ tgt=i386; \
end=le; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Then adapting indentation in helper_vmload() to pass checkpatch.pl.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/ops_sse.h | 12 ++---
target/i386/tcg/seg_helper.h | 12 ++---
linux-user/vm86.c | 4 +-
target/i386/tcg/mem_helper.c | 8 ++--
target/i386/tcg/mpx_helper.c | 28 +++++------
target/i386/tcg/seg_helper.c | 16 +++----
target/i386/tcg/system/excp_helper.c | 8 ++--
target/i386/tcg/system/svm_helper.c | 69 +++++++++++++++-------------
8 files changed, 80 insertions(+), 77 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index a2e4d480399..213db53382c 100644
--- a/target/i386/ops_sse.h
+++ b/target/i386/ops_sse.h
@@ -2326,7 +2326,7 @@ void glue(helper_vpmaskmovd_st, SUFFIX)(CPUX86State *env,
for (i = 0; i < (2 << SHIFT); i++) {
if (v->L(i) >> 31) {
- cpu_stl_data_ra(env, a0 + i * 4, s->L(i), GETPC());
+ cpu_stl_le_data_ra(env, a0 + i * 4, s->L(i), GETPC());
}
}
}
@@ -2338,7 +2338,7 @@ void glue(helper_vpmaskmovq_st, SUFFIX)(CPUX86State *env,
for (i = 0; i < (1 << SHIFT); i++) {
if (v->Q(i) >> 63) {
- cpu_stq_data_ra(env, a0 + i * 8, s->Q(i), GETPC());
+ cpu_stq_le_data_ra(env, a0 + i * 8, s->Q(i), GETPC());
}
}
}
@@ -2369,7 +2369,7 @@ void glue(helper_vpgatherdd, SUFFIX)(CPUX86State *env,
if (v->L(i) >> 31) {
target_ulong addr = a0
+ ((target_ulong)(int32_t)s->L(i) << scale);
- d->L(i) = cpu_ldl_data_ra(env, addr, GETPC());
+ d->L(i) = cpu_ldl_le_data_ra(env, addr, GETPC());
}
v->L(i) = 0;
}
@@ -2383,7 +2383,7 @@ void glue(helper_vpgatherdq, SUFFIX)(CPUX86State *env,
if (v->Q(i) >> 63) {
target_ulong addr = a0
+ ((target_ulong)(int32_t)s->L(i) << scale);
- d->Q(i) = cpu_ldq_data_ra(env, addr, GETPC());
+ d->Q(i) = cpu_ldq_le_data_ra(env, addr, GETPC());
}
v->Q(i) = 0;
}
@@ -2397,7 +2397,7 @@ void glue(helper_vpgatherqd, SUFFIX)(CPUX86State *env,
if (v->L(i) >> 31) {
target_ulong addr = a0
+ ((target_ulong)(int64_t)s->Q(i) << scale);
- d->L(i) = cpu_ldl_data_ra(env, addr, GETPC());
+ d->L(i) = cpu_ldl_le_data_ra(env, addr, GETPC());
}
v->L(i) = 0;
}
@@ -2415,7 +2415,7 @@ void glue(helper_vpgatherqq, SUFFIX)(CPUX86State *env,
if (v->Q(i) >> 63) {
target_ulong addr = a0
+ ((target_ulong)(int64_t)s->Q(i) << scale);
- d->Q(i) = cpu_ldq_data_ra(env, addr, GETPC());
+ d->Q(i) = cpu_ldq_le_data_ra(env, addr, GETPC());
}
v->Q(i) = 0;
}
diff --git a/target/i386/tcg/seg_helper.h b/target/i386/tcg/seg_helper.h
index ea98e1a98ed..20ce47d62d9 100644
--- a/target/i386/tcg/seg_helper.h
+++ b/target/i386/tcg/seg_helper.h
@@ -40,18 +40,18 @@ int cpu_mmu_index_kernel(CPUX86State *env);
* and use *_mmuidx_ra directly.
*/
#define cpu_lduw_kernel_ra(e, p, r) \
- cpu_lduw_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)
+ cpu_lduw_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)
#define cpu_ldl_kernel_ra(e, p, r) \
- cpu_ldl_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)
+ cpu_ldl_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)
#define cpu_ldq_kernel_ra(e, p, r) \
- cpu_ldq_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)
+ cpu_ldq_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r)
#define cpu_stw_kernel_ra(e, p, v, r) \
- cpu_stw_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)
+ cpu_stw_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)
#define cpu_stl_kernel_ra(e, p, v, r) \
- cpu_stl_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)
+ cpu_stl_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)
#define cpu_stq_kernel_ra(e, p, v, r) \
- cpu_stq_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)
+ cpu_stq_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r)
#define cpu_lduw_kernel(e, p) cpu_lduw_kernel_ra(e, p, 0)
#define cpu_ldl_kernel(e, p) cpu_ldl_kernel_ra(e, p, 0)
diff --git a/linux-user/vm86.c b/linux-user/vm86.c
index 5091d53fb84..4e120875a06 100644
--- a/linux-user/vm86.c
+++ b/linux-user/vm86.c
@@ -44,7 +44,7 @@ static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)
static inline void vm_putw(CPUX86State *env, uint32_t segptr,
unsigned int reg16, unsigned int val)
{
- cpu_stw_data(env, segptr + (reg16 & 0xffff), val);
+ cpu_stw_le_data(env, segptr + (reg16 & 0xffff), val);
}
void save_v86_state(CPUX86State *env)
@@ -157,7 +157,7 @@ static void do_int(CPUX86State *env, int intno)
&ts->vm86plus.int21_revectored))
goto cannot_handle;
int_addr = (intno << 2);
- segoffs = cpu_ldl_data(env, int_addr);
+ segoffs = cpu_ldl_le_data(env, int_addr);
if ((segoffs >> 16) == TARGET_BIOSSEG)
goto cannot_handle;
LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c
index 9e7c2d80293..c15a32d60ad 100644
--- a/target/i386/tcg/mem_helper.c
+++ b/target/i386/tcg/mem_helper.c
@@ -30,8 +30,8 @@ void helper_boundw(CPUX86State *env, target_ulong a0, int v)
{
int low, high;
- low = cpu_ldsw_data_ra(env, a0, GETPC());
- high = cpu_ldsw_data_ra(env, a0 + 2, GETPC());
+ low = cpu_ldsw_le_data_ra(env, a0, GETPC());
+ high = cpu_ldsw_le_data_ra(env, a0 + 2, GETPC());
v = (int16_t)v;
if (v < low || v > high) {
if (env->hflags & HF_MPX_EN_MASK) {
@@ -45,8 +45,8 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v)
{
int low, high;
- low = cpu_ldl_data_ra(env, a0, GETPC());
- high = cpu_ldl_data_ra(env, a0 + 4, GETPC());
+ low = cpu_ldl_le_data_ra(env, a0, GETPC());
+ high = cpu_ldl_le_data_ra(env, a0 + 4, GETPC());
if (v < low || v > high) {
if (env->hflags & HF_MPX_EN_MASK) {
env->bndcs_regs.sts = 0;
diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c
index fa8abcc4820..73d33bf5e4a 100644
--- a/target/i386/tcg/mpx_helper.c
+++ b/target/i386/tcg/mpx_helper.c
@@ -44,7 +44,7 @@ static uint64_t lookup_bte64(CPUX86State *env, uint64_t base, uintptr_t ra)
}
bde = (extract64(base, 20, 28) << 3) + (extract64(bndcsr, 20, 44) << 12);
- bt = cpu_ldq_data_ra(env, bde, ra);
+ bt = cpu_ldq_le_data_ra(env, bde, ra);
if ((bt & 1) == 0) {
env->bndcs_regs.sts = bde | 2;
raise_exception_ra(env, EXCP05_BOUND, ra);
@@ -64,7 +64,7 @@ static uint32_t lookup_bte32(CPUX86State *env, uint32_t base, uintptr_t ra)
}
bde = (extract32(base, 12, 20) << 2) + (bndcsr & TARGET_PAGE_MASK);
- bt = cpu_ldl_data_ra(env, bde, ra);
+ bt = cpu_ldl_le_data_ra(env, bde, ra);
if ((bt & 1) == 0) {
env->bndcs_regs.sts = bde | 2;
raise_exception_ra(env, EXCP05_BOUND, ra);
@@ -79,9 +79,9 @@ uint64_t helper_bndldx64(CPUX86State *env, target_ulong base, target_ulong ptr)
uint64_t bte, lb, ub, pt;
bte = lookup_bte64(env, base, ra);
- lb = cpu_ldq_data_ra(env, bte, ra);
- ub = cpu_ldq_data_ra(env, bte + 8, ra);
- pt = cpu_ldq_data_ra(env, bte + 16, ra);
+ lb = cpu_ldq_le_data_ra(env, bte, ra);
+ ub = cpu_ldq_le_data_ra(env, bte + 8, ra);
+ pt = cpu_ldq_le_data_ra(env, bte + 16, ra);
if (pt != ptr) {
lb = ub = 0;
@@ -96,9 +96,9 @@ uint64_t helper_bndldx32(CPUX86State *env, target_ulong base, target_ulong ptr)
uint32_t bte, lb, ub, pt;
bte = lookup_bte32(env, base, ra);
- lb = cpu_ldl_data_ra(env, bte, ra);
- ub = cpu_ldl_data_ra(env, bte + 4, ra);
- pt = cpu_ldl_data_ra(env, bte + 8, ra);
+ lb = cpu_ldl_le_data_ra(env, bte, ra);
+ ub = cpu_ldl_le_data_ra(env, bte + 4, ra);
+ pt = cpu_ldl_le_data_ra(env, bte + 8, ra);
if (pt != ptr) {
lb = ub = 0;
@@ -113,9 +113,9 @@ void helper_bndstx64(CPUX86State *env, target_ulong base, target_ulong ptr,
uint64_t bte;
bte = lookup_bte64(env, base, ra);
- cpu_stq_data_ra(env, bte, lb, ra);
- cpu_stq_data_ra(env, bte + 8, ub, ra);
- cpu_stq_data_ra(env, bte + 16, ptr, ra);
+ cpu_stq_le_data_ra(env, bte, lb, ra);
+ cpu_stq_le_data_ra(env, bte + 8, ub, ra);
+ cpu_stq_le_data_ra(env, bte + 16, ptr, ra);
}
void helper_bndstx32(CPUX86State *env, target_ulong base, target_ulong ptr,
@@ -125,9 +125,9 @@ void helper_bndstx32(CPUX86State *env, target_ulong base, target_ulong ptr,
uint32_t bte;
bte = lookup_bte32(env, base, ra);
- cpu_stl_data_ra(env, bte, lb, ra);
- cpu_stl_data_ra(env, bte + 4, ub, ra);
- cpu_stl_data_ra(env, bte + 8, ptr, ra);
+ cpu_stl_le_data_ra(env, bte, lb, ra);
+ cpu_stl_le_data_ra(env, bte + 4, ub, ra);
+ cpu_stl_le_data_ra(env, bte + 8, ptr, ra);
}
void helper_bnd_jmp(CPUX86State *env)
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index 227336c4ef2..58aac720119 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -65,20 +65,20 @@ typedef struct StackAccess
static void pushw(StackAccess *sa, uint16_t val)
{
sa->sp -= 2;
- cpu_stw_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask),
+ cpu_stw_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask),
val, sa->mmu_index, sa->ra);
}
static void pushl(StackAccess *sa, uint32_t val)
{
sa->sp -= 4;
- cpu_stl_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask),
+ cpu_stl_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask),
val, sa->mmu_index, sa->ra);
}
static uint16_t popw(StackAccess *sa)
{
- uint16_t ret = cpu_lduw_mmuidx_ra(sa->env,
+ uint16_t ret = cpu_lduw_le_mmuidx_ra(sa->env,
sa->ss_base + (sa->sp & sa->sp_mask),
sa->mmu_index, sa->ra);
sa->sp += 2;
@@ -87,7 +87,7 @@ static uint16_t popw(StackAccess *sa)
static uint32_t popl(StackAccess *sa)
{
- uint32_t ret = cpu_ldl_mmuidx_ra(sa->env,
+ uint32_t ret = cpu_ldl_le_mmuidx_ra(sa->env,
sa->ss_base + (sa->sp & sa->sp_mask),
sa->mmu_index, sa->ra);
sa->sp += 4;
@@ -905,12 +905,12 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
static void pushq(StackAccess *sa, uint64_t val)
{
sa->sp -= 8;
- cpu_stq_mmuidx_ra(sa->env, sa->sp, val, sa->mmu_index, sa->ra);
+ cpu_stq_le_mmuidx_ra(sa->env, sa->sp, val, sa->mmu_index, sa->ra);
}
static uint64_t popq(StackAccess *sa)
{
- uint64_t ret = cpu_ldq_mmuidx_ra(sa->env, sa->sp, sa->mmu_index, sa->ra);
+ uint64_t ret = cpu_ldq_le_mmuidx_ra(sa->env, sa->sp, sa->mmu_index, sa->ra);
sa->sp += 8;
return ret;
}
@@ -1887,7 +1887,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
pushl(&sa, env->segs[R_SS].selector);
pushl(&sa, env->regs[R_ESP]);
for (i = param_count - 1; i >= 0; i--) {
- val = cpu_ldl_data_ra(env,
+ val = cpu_ldl_le_data_ra(env,
old_ssp + ((env->regs[R_ESP] + i * 4) & old_sp_mask),
GETPC());
pushl(&sa, val);
@@ -1896,7 +1896,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
pushw(&sa, env->segs[R_SS].selector);
pushw(&sa, env->regs[R_ESP]);
for (i = param_count - 1; i >= 0; i--) {
- val = cpu_lduw_data_ra(env,
+ val = cpu_lduw_le_data_ra(env,
old_ssp + ((env->regs[R_ESP] + i * 2) & old_sp_mask),
GETPC());
pushw(&sa, val);
diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c
index f622b5d588e..d7ea77c8558 100644
--- a/target/i386/tcg/system/excp_helper.c
+++ b/target/i386/tcg/system/excp_helper.c
@@ -90,7 +90,7 @@ static inline uint32_t ptw_ldl(const PTETranslate *in, uint64_t ra)
if (likely(in->haddr)) {
return ldl_p(in->haddr);
}
- return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);
+ return cpu_ldl_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);
}
static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra)
@@ -98,7 +98,7 @@ static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra)
if (likely(in->haddr)) {
return ldq_p(in->haddr);
}
- return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);
+ return cpu_ldq_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra);
}
/*
@@ -116,9 +116,9 @@ static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t new)
cpu_exec_end(cpu);
/* Does x86 really perform a rmw cycle on mmio for ptw? */
start_exclusive();
- cmp = cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0);
+ cmp = cpu_ldl_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0);
if (cmp == old) {
- cpu_stl_mmuidx_ra(in->env, in->gaddr, new, in->ptw_idx, 0);
+ cpu_stl_le_mmuidx_ra(in->env, in->gaddr, new, in->ptw_idx, 0);
}
end_exclusive();
cpu_exec_start(cpu);
diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/svm_helper.c
index 4b86796518f..3e236094d6f 100644
--- a/target/i386/tcg/system/svm_helper.c
+++ b/target/i386/tcg/system/svm_helper.c
@@ -30,13 +30,13 @@
static void svm_save_seg(CPUX86State *env, int mmu_idx, hwaddr addr,
const SegmentCache *sc)
{
- cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector),
+ cpu_stw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector),
sc->selector, mmu_idx, 0);
- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base),
+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base),
sc->base, mmu_idx, 0);
- cpu_stl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit),
+ cpu_stl_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit),
sc->limit, mmu_idx, 0);
- cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib),
+ cpu_stw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib),
((sc->flags >> 8) & 0xff)
| ((sc->flags >> 12) & 0x0f00),
mmu_idx, 0);
@@ -58,16 +58,16 @@ static void svm_load_seg(CPUX86State *env, int mmu_idx, hwaddr addr,
unsigned int flags;
sc->selector =
- cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector),
+ cpu_lduw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector),
mmu_idx, 0);
sc->base =
- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base),
+ cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base),
mmu_idx, 0);
sc->limit =
- cpu_ldl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit),
+ cpu_ldl_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit),
mmu_idx, 0);
flags =
- cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib),
+ cpu_lduw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib),
mmu_idx, 0);
sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
@@ -507,32 +507,35 @@ void helper_vmload(CPUX86State *env, int aflag)
#ifdef TARGET_X86_64
env->kernelgsbase =
- cpu_ldq_mmuidx_ra(env,
- addr + offsetof(struct vmcb, save.kernel_gs_base),
- mmu_idx, 0);
+ cpu_ldq_le_mmuidx_ra(env,
+ addr + offsetof(struct vmcb, save.kernel_gs_base),
+ mmu_idx, 0);
env->lstar =
- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar),
- mmu_idx, 0);
+ cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar),
+ mmu_idx, 0);
env->cstar =
- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar),
- mmu_idx, 0);
+ cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar),
+ mmu_idx, 0);
env->fmask =
- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask),
- mmu_idx, 0);
+ cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask),
+ mmu_idx, 0);
svm_canonicalization(env, &env->kernelgsbase);
#endif
env->star =
- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star),
- mmu_idx, 0);
+ cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star),
+ mmu_idx, 0);
env->sysenter_cs =
- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_cs),
- mmu_idx, 0);
+ cpu_ldq_le_mmuidx_ra(env,
+ addr + offsetof(struct vmcb, save.sysenter_cs),
+ mmu_idx, 0);
env->sysenter_esp =
- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_esp),
- mmu_idx, 0);
+ cpu_ldq_le_mmuidx_ra(env,
+ addr + offsetof(struct vmcb, save.sysenter_esp),
+ mmu_idx, 0);
env->sysenter_eip =
- cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_eip),
- mmu_idx, 0);
+ cpu_ldq_le_mmuidx_ra(env,
+ addr + offsetof(struct vmcb, save.sysenter_eip),
+ mmu_idx, 0);
}
void helper_vmsave(CPUX86State *env, int aflag)
@@ -567,22 +570,22 @@ void helper_vmsave(CPUX86State *env, int aflag)
&env->ldt);
#ifdef TARGET_X86_64
- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.kernel_gs_base),
+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.kernel_gs_base),
env->kernelgsbase, mmu_idx, 0);
- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar),
+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar),
env->lstar, mmu_idx, 0);
- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar),
+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar),
env->cstar, mmu_idx, 0);
- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask),
+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask),
env->fmask, mmu_idx, 0);
#endif
- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star),
+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star),
env->star, mmu_idx, 0);
- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_cs),
+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_cs),
env->sysenter_cs, mmu_idx, 0);
- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_esp),
+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_esp),
env->sysenter_esp, mmu_idx, 0);
- cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_eip),
+ cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_eip),
env->sysenter_eip, mmu_idx, 0);
}
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 03/22] target/riscv: Use little-endian variant of cpu_ld/st_data*() for vector
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 01/22] target/hexagon: Use little-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 02/22] target/i386: " Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 04/22] target/rx: Use little-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé
` (18 subsequent siblings)
21 siblings, 0 replies; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Daniel Henrique Barboza,
Palmer Dabbelt, Alistair Francis, Weiwei Li, Liu Zhiwei
RISC-V vector "elements are simply packed in order from
the least-signicant to most-signicant bits of the vector
register" [*] which is little endianness, therefore the
cpu_ld/st_data*() definitions expand to the little endian
declarations. Use the explicit little-endian variants.
[*] RISC-V "V" Vector Extension v1.0
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/vector_helper.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 2de3358ee86..caa8dd9c125 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -193,9 +193,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host) \
}
GEN_VEXT_LD_ELEM(lde_b, uint8_t, H1, ldub)
-GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw)
-GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl)
-GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq)
+GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw_le)
+GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl_le)
+GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq_le)
#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \
static inline QEMU_ALWAYS_INLINE \
@@ -214,9 +214,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host) \
}
GEN_VEXT_ST_ELEM(ste_b, uint8_t, H1, stb)
-GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw)
-GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl)
-GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq)
+GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw_le)
+GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl_le)
+GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq_le)
static inline QEMU_ALWAYS_INLINE void
vext_continuous_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb,
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 04/22] target/rx: Use little-endian variant of cpu_ld/st_data*()
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 03/22] target/riscv: Use little-endian variant of cpu_ld/st_data*() for vector Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 05/22] target/tricore: " Philippe Mathieu-Daudé
` (17 subsequent siblings)
21 siblings, 0 replies; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Yoshinori Sato
We only build the RX target using little endianness order,
therefore the cpu_ld/st_data*() definitions expand to the little
endian declarations. Use the explicit little-endian variants.
Mechanical change running:
$ tgt=rx; \
end=le; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/rx/helper.c | 14 +++++++-------
target/rx/op_helper.c | 6 +++---
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/rx/helper.c b/target/rx/helper.c
index e9a7aaf610d..83cd491eb4a 100644
--- a/target/rx/helper.c
+++ b/target/rx/helper.c
@@ -68,10 +68,10 @@ void rx_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n");
} else if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) {
env->isp -= 4;
- cpu_stl_data(env, env->isp, save_psw);
+ cpu_stl_le_data(env, env->isp, save_psw);
env->isp -= 4;
- cpu_stl_data(env, env->isp, env->pc);
- env->pc = cpu_ldl_data(env, env->intb + env->ack_irq * 4);
+ cpu_stl_le_data(env, env->isp, env->pc);
+ env->pc = cpu_ldl_le_data(env, env->intb + env->ack_irq * 4);
env->psw_ipl = env->ack_ipl;
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
qemu_set_irq(env->ack, env->ack_irq);
@@ -82,14 +82,14 @@ void rx_cpu_do_interrupt(CPUState *cs)
const char *expname = "unknown exception";
env->isp -= 4;
- cpu_stl_data(env, env->isp, save_psw);
+ cpu_stl_le_data(env, env->isp, save_psw);
env->isp -= 4;
- cpu_stl_data(env, env->isp, env->pc);
+ cpu_stl_le_data(env, env->isp, env->pc);
if (vec < 0x100) {
- env->pc = cpu_ldl_data(env, 0xffffff80 + vec * 4);
+ env->pc = cpu_ldl_le_data(env, 0xffffff80 + vec * 4);
} else {
- env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4);
+ env->pc = cpu_ldl_le_data(env, env->intb + (vec & 0xff) * 4);
}
if (vec == 30) {
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index 2b190a4b2cf..ca3e9e85fc7 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -217,20 +217,20 @@ void helper_scmpu(CPURXState *env)
static uint32_t (* const cpu_ldufn[])(CPUArchState *env,
abi_ptr ptr,
uintptr_t retaddr) = {
- cpu_ldub_data_ra, cpu_lduw_data_ra, cpu_ldl_data_ra,
+ cpu_ldub_data_ra, cpu_lduw_le_data_ra, cpu_ldl_le_data_ra,
};
static uint32_t (* const cpu_ldfn[])(CPUArchState *env,
abi_ptr ptr,
uintptr_t retaddr) = {
- cpu_ldub_data_ra, cpu_lduw_data_ra, cpu_ldl_data_ra,
+ cpu_ldub_data_ra, cpu_lduw_le_data_ra, cpu_ldl_le_data_ra,
};
static void (* const cpu_stfn[])(CPUArchState *env,
abi_ptr ptr,
uint32_t val,
uintptr_t retaddr) = {
- cpu_stb_data_ra, cpu_stw_data_ra, cpu_stl_data_ra,
+ cpu_stb_data_ra, cpu_stw_le_data_ra, cpu_stl_le_data_ra,
};
void helper_sstr(CPURXState *env, uint32_t sz)
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 05/22] target/tricore: Use little-endian variant of cpu_ld/st_data*()
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 04/22] target/rx: Use little-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 06/22] target/hppa: Use big-endian " Philippe Mathieu-Daudé
` (16 subsequent siblings)
21 siblings, 0 replies; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Bastian Koppelmann
We only build the TriCore target using little endianness order,
therefore the cpu_ld/st_data*() definitions expand to the little
endian declarations. Use the explicit little-endian variants.
Mechanical change running:
$ tgt=tricore; \
end=le; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Then adapting spaces style manually to pass checkpatch.pl.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/op_helper.c | 152 ++++++++++++++++++-------------------
1 file changed, 76 insertions(+), 76 deletions(-)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 2c8281a67e0..fde2c0f8383 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2451,84 +2451,84 @@ static bool cdc_zero(uint32_t *psw)
static void save_context_upper(CPUTriCoreState *env, uint32_t ea)
{
- cpu_stl_data(env, ea, env->PCXI);
- cpu_stl_data(env, ea+4, psw_read(env));
- cpu_stl_data(env, ea+8, env->gpr_a[10]);
- cpu_stl_data(env, ea+12, env->gpr_a[11]);
- cpu_stl_data(env, ea+16, env->gpr_d[8]);
- cpu_stl_data(env, ea+20, env->gpr_d[9]);
- cpu_stl_data(env, ea+24, env->gpr_d[10]);
- cpu_stl_data(env, ea+28, env->gpr_d[11]);
- cpu_stl_data(env, ea+32, env->gpr_a[12]);
- cpu_stl_data(env, ea+36, env->gpr_a[13]);
- cpu_stl_data(env, ea+40, env->gpr_a[14]);
- cpu_stl_data(env, ea+44, env->gpr_a[15]);
- cpu_stl_data(env, ea+48, env->gpr_d[12]);
- cpu_stl_data(env, ea+52, env->gpr_d[13]);
- cpu_stl_data(env, ea+56, env->gpr_d[14]);
- cpu_stl_data(env, ea+60, env->gpr_d[15]);
+ cpu_stl_le_data(env, ea, env->PCXI);
+ cpu_stl_le_data(env, ea + 4, psw_read(env));
+ cpu_stl_le_data(env, ea + 8, env->gpr_a[10]);
+ cpu_stl_le_data(env, ea + 12, env->gpr_a[11]);
+ cpu_stl_le_data(env, ea + 16, env->gpr_d[8]);
+ cpu_stl_le_data(env, ea + 20, env->gpr_d[9]);
+ cpu_stl_le_data(env, ea + 24, env->gpr_d[10]);
+ cpu_stl_le_data(env, ea + 28, env->gpr_d[11]);
+ cpu_stl_le_data(env, ea + 32, env->gpr_a[12]);
+ cpu_stl_le_data(env, ea + 36, env->gpr_a[13]);
+ cpu_stl_le_data(env, ea + 40, env->gpr_a[14]);
+ cpu_stl_le_data(env, ea + 44, env->gpr_a[15]);
+ cpu_stl_le_data(env, ea + 48, env->gpr_d[12]);
+ cpu_stl_le_data(env, ea + 52, env->gpr_d[13]);
+ cpu_stl_le_data(env, ea + 56, env->gpr_d[14]);
+ cpu_stl_le_data(env, ea + 60, env->gpr_d[15]);
}
static void save_context_lower(CPUTriCoreState *env, uint32_t ea)
{
- cpu_stl_data(env, ea, env->PCXI);
- cpu_stl_data(env, ea+4, env->gpr_a[11]);
- cpu_stl_data(env, ea+8, env->gpr_a[2]);
- cpu_stl_data(env, ea+12, env->gpr_a[3]);
- cpu_stl_data(env, ea+16, env->gpr_d[0]);
- cpu_stl_data(env, ea+20, env->gpr_d[1]);
- cpu_stl_data(env, ea+24, env->gpr_d[2]);
- cpu_stl_data(env, ea+28, env->gpr_d[3]);
- cpu_stl_data(env, ea+32, env->gpr_a[4]);
- cpu_stl_data(env, ea+36, env->gpr_a[5]);
- cpu_stl_data(env, ea+40, env->gpr_a[6]);
- cpu_stl_data(env, ea+44, env->gpr_a[7]);
- cpu_stl_data(env, ea+48, env->gpr_d[4]);
- cpu_stl_data(env, ea+52, env->gpr_d[5]);
- cpu_stl_data(env, ea+56, env->gpr_d[6]);
- cpu_stl_data(env, ea+60, env->gpr_d[7]);
+ cpu_stl_le_data(env, ea, env->PCXI);
+ cpu_stl_le_data(env, ea + 4, env->gpr_a[11]);
+ cpu_stl_le_data(env, ea + 8, env->gpr_a[2]);
+ cpu_stl_le_data(env, ea + 12, env->gpr_a[3]);
+ cpu_stl_le_data(env, ea + 16, env->gpr_d[0]);
+ cpu_stl_le_data(env, ea + 20, env->gpr_d[1]);
+ cpu_stl_le_data(env, ea + 24, env->gpr_d[2]);
+ cpu_stl_le_data(env, ea + 28, env->gpr_d[3]);
+ cpu_stl_le_data(env, ea + 32, env->gpr_a[4]);
+ cpu_stl_le_data(env, ea + 36, env->gpr_a[5]);
+ cpu_stl_le_data(env, ea + 40, env->gpr_a[6]);
+ cpu_stl_le_data(env, ea + 44, env->gpr_a[7]);
+ cpu_stl_le_data(env, ea + 48, env->gpr_d[4]);
+ cpu_stl_le_data(env, ea + 52, env->gpr_d[5]);
+ cpu_stl_le_data(env, ea + 56, env->gpr_d[6]);
+ cpu_stl_le_data(env, ea + 60, env->gpr_d[7]);
}
static void restore_context_upper(CPUTriCoreState *env, uint32_t ea,
uint32_t *new_PCXI, uint32_t *new_PSW)
{
- *new_PCXI = cpu_ldl_data(env, ea);
- *new_PSW = cpu_ldl_data(env, ea+4);
- env->gpr_a[10] = cpu_ldl_data(env, ea+8);
- env->gpr_a[11] = cpu_ldl_data(env, ea+12);
- env->gpr_d[8] = cpu_ldl_data(env, ea+16);
- env->gpr_d[9] = cpu_ldl_data(env, ea+20);
- env->gpr_d[10] = cpu_ldl_data(env, ea+24);
- env->gpr_d[11] = cpu_ldl_data(env, ea+28);
- env->gpr_a[12] = cpu_ldl_data(env, ea+32);
- env->gpr_a[13] = cpu_ldl_data(env, ea+36);
- env->gpr_a[14] = cpu_ldl_data(env, ea+40);
- env->gpr_a[15] = cpu_ldl_data(env, ea+44);
- env->gpr_d[12] = cpu_ldl_data(env, ea+48);
- env->gpr_d[13] = cpu_ldl_data(env, ea+52);
- env->gpr_d[14] = cpu_ldl_data(env, ea+56);
- env->gpr_d[15] = cpu_ldl_data(env, ea+60);
+ *new_PCXI = cpu_ldl_le_data(env, ea);
+ *new_PSW = cpu_ldl_le_data(env, ea + 4);
+ env->gpr_a[10] = cpu_ldl_le_data(env, ea + 8);
+ env->gpr_a[11] = cpu_ldl_le_data(env, ea + 12);
+ env->gpr_d[8] = cpu_ldl_le_data(env, ea + 16);
+ env->gpr_d[9] = cpu_ldl_le_data(env, ea + 20);
+ env->gpr_d[10] = cpu_ldl_le_data(env, ea + 24);
+ env->gpr_d[11] = cpu_ldl_le_data(env, ea + 28);
+ env->gpr_a[12] = cpu_ldl_le_data(env, ea + 32);
+ env->gpr_a[13] = cpu_ldl_le_data(env, ea + 36);
+ env->gpr_a[14] = cpu_ldl_le_data(env, ea + 40);
+ env->gpr_a[15] = cpu_ldl_le_data(env, ea + 44);
+ env->gpr_d[12] = cpu_ldl_le_data(env, ea + 48);
+ env->gpr_d[13] = cpu_ldl_le_data(env, ea + 52);
+ env->gpr_d[14] = cpu_ldl_le_data(env, ea + 56);
+ env->gpr_d[15] = cpu_ldl_le_data(env, ea + 60);
}
static void restore_context_lower(CPUTriCoreState *env, uint32_t ea,
uint32_t *ra, uint32_t *pcxi)
{
- *pcxi = cpu_ldl_data(env, ea);
- *ra = cpu_ldl_data(env, ea+4);
- env->gpr_a[2] = cpu_ldl_data(env, ea+8);
- env->gpr_a[3] = cpu_ldl_data(env, ea+12);
- env->gpr_d[0] = cpu_ldl_data(env, ea+16);
- env->gpr_d[1] = cpu_ldl_data(env, ea+20);
- env->gpr_d[2] = cpu_ldl_data(env, ea+24);
- env->gpr_d[3] = cpu_ldl_data(env, ea+28);
- env->gpr_a[4] = cpu_ldl_data(env, ea+32);
- env->gpr_a[5] = cpu_ldl_data(env, ea+36);
- env->gpr_a[6] = cpu_ldl_data(env, ea+40);
- env->gpr_a[7] = cpu_ldl_data(env, ea+44);
- env->gpr_d[4] = cpu_ldl_data(env, ea+48);
- env->gpr_d[5] = cpu_ldl_data(env, ea+52);
- env->gpr_d[6] = cpu_ldl_data(env, ea+56);
- env->gpr_d[7] = cpu_ldl_data(env, ea+60);
+ *pcxi = cpu_ldl_le_data(env, ea);
+ *ra = cpu_ldl_le_data(env, ea + 4);
+ env->gpr_a[2] = cpu_ldl_le_data(env, ea + 8);
+ env->gpr_a[3] = cpu_ldl_le_data(env, ea + 12);
+ env->gpr_d[0] = cpu_ldl_le_data(env, ea + 16);
+ env->gpr_d[1] = cpu_ldl_le_data(env, ea + 20);
+ env->gpr_d[2] = cpu_ldl_le_data(env, ea + 24);
+ env->gpr_d[3] = cpu_ldl_le_data(env, ea + 28);
+ env->gpr_a[4] = cpu_ldl_le_data(env, ea + 32);
+ env->gpr_a[5] = cpu_ldl_le_data(env, ea + 36);
+ env->gpr_a[6] = cpu_ldl_le_data(env, ea + 40);
+ env->gpr_a[7] = cpu_ldl_le_data(env, ea + 44);
+ env->gpr_d[4] = cpu_ldl_le_data(env, ea + 48);
+ env->gpr_d[5] = cpu_ldl_le_data(env, ea + 52);
+ env->gpr_d[6] = cpu_ldl_le_data(env, ea + 56);
+ env->gpr_d[7] = cpu_ldl_le_data(env, ea + 60);
}
void helper_call(CPUTriCoreState *env, uint32_t next_pc)
@@ -2566,7 +2566,7 @@ void helper_call(CPUTriCoreState *env, uint32_t next_pc)
ea = ((env->FCX & MASK_FCX_FCXS) << 12) +
((env->FCX & MASK_FCX_FCXO) << 6);
/* new_FCX = M(EA, word); */
- new_FCX = cpu_ldl_data(env, ea);
+ new_FCX = cpu_ldl_le_data(env, ea);
/* M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],
A[12], A[13], A[14], A[15], D[12], D[13], D[14],
D[15]}; */
@@ -2632,7 +2632,7 @@ void helper_ret(CPUTriCoreState *env)
A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
restore_context_upper(env, ea, &new_PCXI, &new_PSW);
/* M(EA, word) = FCX; */
- cpu_stl_data(env, ea, env->FCX);
+ cpu_stl_le_data(env, ea, env->FCX);
/* FCX[19: 0] = PCXI[19: 0]; */
env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
/* PCXI = new_PCXI; */
@@ -2662,7 +2662,7 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9)
ea = ((env->FCX & 0xf0000) << 12) + ((env->FCX & 0xffff) << 6);
/* new_FCX = M(EA, word); */
- new_FCX = cpu_ldl_data(env, ea);
+ new_FCX = cpu_ldl_le_data(env, ea);
/* M(EA, 16 * word) = {PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[3], A[4]
, A[5], A[6], A[7], D[4], D[5], D[6], D[7]}; */
save_context_lower(env, ea);
@@ -2726,7 +2726,7 @@ void helper_rfe(CPUTriCoreState *env)
A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
restore_context_upper(env, ea, &new_PCXI, &new_PSW);
/* M(EA, word) = FCX;*/
- cpu_stl_data(env, ea, env->FCX);
+ cpu_stl_le_data(env, ea, env->FCX);
/* FCX[19: 0] = PCXI[19: 0]; */
env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
/* PCXI = new_PCXI; */
@@ -2744,10 +2744,10 @@ void helper_rfm(CPUTriCoreState *env)
icr_set_ccpn(env, pcxi_get_pcpn(env));
/* {PCXI, PSW, A[10], A[11]} = M(DCX, 4 * word); */
- env->PCXI = cpu_ldl_data(env, env->DCX);
- psw_write(env, cpu_ldl_data(env, env->DCX+4));
- env->gpr_a[10] = cpu_ldl_data(env, env->DCX+8);
- env->gpr_a[11] = cpu_ldl_data(env, env->DCX+12);
+ env->PCXI = cpu_ldl_le_data(env, env->DCX);
+ psw_write(env, cpu_ldl_le_data(env, env->DCX+4));
+ env->gpr_a[10] = cpu_ldl_le_data(env, env->DCX+8);
+ env->gpr_a[11] = cpu_ldl_le_data(env, env->DCX+12);
if (tricore_has_feature(env, TRICORE_FEATURE_131)) {
env->DBGTCR = 0;
@@ -2794,7 +2794,7 @@ void helper_svlcx(CPUTriCoreState *env)
ea = ((env->FCX & MASK_FCX_FCXS) << 12) +
((env->FCX & MASK_FCX_FCXO) << 6);
/* new_FCX = M(EA, word); */
- new_FCX = cpu_ldl_data(env, ea);
+ new_FCX = cpu_ldl_le_data(env, ea);
/* M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],
A[12], A[13], A[14], A[15], D[12], D[13], D[14],
D[15]}; */
@@ -2837,7 +2837,7 @@ void helper_svucx(CPUTriCoreState *env)
ea = ((env->FCX & MASK_FCX_FCXS) << 12) +
((env->FCX & MASK_FCX_FCXO) << 6);
/* new_FCX = M(EA, word); */
- new_FCX = cpu_ldl_data(env, ea);
+ new_FCX = cpu_ldl_le_data(env, ea);
/* M(EA, 16 * word) = {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11],
A[12], A[13], A[14], A[15], D[12], D[13], D[14],
D[15]}; */
@@ -2887,9 +2887,9 @@ void helper_rslcx(CPUTriCoreState *env)
A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
restore_context_lower(env, ea, &env->gpr_a[11], &new_PCXI);
/* M(EA, word) = FCX; */
- cpu_stl_data(env, ea, env->FCX);
+ cpu_stl_le_data(env, ea, env->FCX);
/* M(EA, word) = FCX; */
- cpu_stl_data(env, ea, env->FCX);
+ cpu_stl_le_data(env, ea, env->FCX);
/* FCX[19: 0] = PCXI[19: 0]; */
env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
/* PCXI = new_PCXI; */
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 06/22] target/hppa: Use big-endian variant of cpu_ld/st_data*()
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 05/22] target/tricore: " Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 07/22] target/m68k: " Philippe Mathieu-Daudé
` (15 subsequent siblings)
21 siblings, 0 replies; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Helge Deller
We only build the HPPA target using big endianness order,
therefore the cpu_ld/st_data*() definitions expand to the big
endian declarations. Use the explicit big-endian variants.
Mechanical change running:
$ tgt=hppa; \
end=be; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/op_helper.c | 44 ++++++++++++++++++++---------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index 0458378abb2..65faf03cd0a 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -107,7 +107,7 @@ static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong val,
cpu_stb_data_ra(env, addr, val, ra);
break;
case 2:
- cpu_stw_data_ra(env, addr, val, ra);
+ cpu_stw_be_data_ra(env, addr, val, ra);
break;
case 1:
/* The 3 byte store must appear atomic. */
@@ -115,11 +115,11 @@ static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong val,
atomic_store_mask32(env, addr, val, 0x00ffffffu, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 16, ra);
- cpu_stw_data_ra(env, addr + 1, val, ra);
+ cpu_stw_be_data_ra(env, addr + 1, val, ra);
}
break;
default:
- cpu_stl_data_ra(env, addr, val, ra);
+ cpu_stl_be_data_ra(env, addr, val, ra);
break;
}
}
@@ -132,7 +132,7 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
cpu_stb_data_ra(env, addr, val, ra);
break;
case 6:
- cpu_stw_data_ra(env, addr, val, ra);
+ cpu_stw_be_data_ra(env, addr, val, ra);
break;
case 5:
/* The 3 byte store must appear atomic. */
@@ -140,11 +140,11 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask32(env, addr, val, 0x00ffffffu, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 16, ra);
- cpu_stw_data_ra(env, addr + 1, val, ra);
+ cpu_stw_be_data_ra(env, addr + 1, val, ra);
}
break;
case 4:
- cpu_stl_data_ra(env, addr, val, ra);
+ cpu_stl_be_data_ra(env, addr, val, ra);
break;
case 3:
/* The 5 byte store must appear atomic. */
@@ -152,7 +152,7 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask64(env, addr, val, 0x000000ffffffffffull, 5, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 32, ra);
- cpu_stl_data_ra(env, addr + 1, val, ra);
+ cpu_stl_be_data_ra(env, addr + 1, val, ra);
}
break;
case 2:
@@ -160,8 +160,8 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
if (parallel) {
atomic_store_mask64(env, addr, val, 0x0000ffffffffffffull, 6, ra);
} else {
- cpu_stw_data_ra(env, addr, val >> 32, ra);
- cpu_stl_data_ra(env, addr + 2, val, ra);
+ cpu_stw_be_data_ra(env, addr, val >> 32, ra);
+ cpu_stl_be_data_ra(env, addr + 2, val, ra);
}
break;
case 1:
@@ -170,12 +170,12 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask64(env, addr, val, 0x00ffffffffffffffull, 7, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 48, ra);
- cpu_stw_data_ra(env, addr + 1, val >> 32, ra);
- cpu_stl_data_ra(env, addr + 3, val, ra);
+ cpu_stw_be_data_ra(env, addr + 1, val >> 32, ra);
+ cpu_stl_be_data_ra(env, addr + 3, val, ra);
}
break;
default:
- cpu_stq_data_ra(env, addr, val, ra);
+ cpu_stq_be_data_ra(env, addr, val, ra);
break;
}
}
@@ -211,12 +211,12 @@ static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong val,
if (parallel) {
atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra);
} else {
- cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
+ cpu_stw_be_data_ra(env, addr - 3, val >> 16, ra);
cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
}
break;
case 2:
- cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
+ cpu_stw_be_data_ra(env, addr - 2, val >> 16, ra);
break;
case 1:
cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
@@ -239,8 +239,8 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask64(env, addr - 7, val,
0xffffffffffffff00ull, 7, ra);
} else {
- cpu_stl_data_ra(env, addr - 7, val >> 32, ra);
- cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
+ cpu_stl_be_data_ra(env, addr - 7, val >> 32, ra);
+ cpu_stw_be_data_ra(env, addr - 3, val >> 16, ra);
cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
}
break;
@@ -250,8 +250,8 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask64(env, addr - 6, val,
0xffffffffffff0000ull, 6, ra);
} else {
- cpu_stl_data_ra(env, addr - 6, val >> 32, ra);
- cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
+ cpu_stl_be_data_ra(env, addr - 6, val >> 32, ra);
+ cpu_stw_be_data_ra(env, addr - 2, val >> 16, ra);
}
break;
case 5:
@@ -260,24 +260,24 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask64(env, addr - 5, val,
0xffffffffff000000ull, 5, ra);
} else {
- cpu_stl_data_ra(env, addr - 5, val >> 32, ra);
+ cpu_stl_be_data_ra(env, addr - 5, val >> 32, ra);
cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
}
break;
case 4:
- cpu_stl_data_ra(env, addr - 4, val >> 32, ra);
+ cpu_stl_be_data_ra(env, addr - 4, val >> 32, ra);
break;
case 3:
/* The 3 byte store must appear atomic. */
if (parallel) {
atomic_store_mask32(env, addr - 3, val >> 32, 0xffffff00u, ra);
} else {
- cpu_stw_data_ra(env, addr - 3, val >> 48, ra);
+ cpu_stw_be_data_ra(env, addr - 3, val >> 48, ra);
cpu_stb_data_ra(env, addr - 1, val >> 40, ra);
}
break;
case 2:
- cpu_stw_data_ra(env, addr - 2, val >> 48, ra);
+ cpu_stw_be_data_ra(env, addr - 2, val >> 48, ra);
break;
case 1:
cpu_stb_data_ra(env, addr - 1, val >> 56, ra);
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 07/22] target/m68k: Use big-endian variant of cpu_ld/st_data*()
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 06/22] target/hppa: Use big-endian " Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-05 20:02 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 08/22] target/s390x: " Philippe Mathieu-Daudé
` (14 subsequent siblings)
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Laurent Vivier
We only build the M68k target using big endianness order,
therefore the cpu_ld/st_data*() definitions expand to the
big endian declarations. Use the explicit big-endian variants.
Mechanical change running:
$ tgt=m68k; \
end=be; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Then adapting indentation in do_stack_frame() to pass checkpatch.pl.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/m68k/fpu_helper.c | 12 +++---
target/m68k/op_helper.c | 91 ++++++++++++++++++++--------------------
2 files changed, 52 insertions(+), 51 deletions(-)
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
index 56012863c85..f49f841d489 100644
--- a/target/m68k/fpu_helper.c
+++ b/target/m68k/fpu_helper.c
@@ -510,8 +510,8 @@ static int cpu_ld_floatx80_ra(CPUM68KState *env, uint32_t addr, FPReg *fp,
uint32_t high;
uint64_t low;
- high = cpu_ldl_data_ra(env, addr, ra);
- low = cpu_ldq_data_ra(env, addr + 4, ra);
+ high = cpu_ldl_be_data_ra(env, addr, ra);
+ low = cpu_ldq_be_data_ra(env, addr + 4, ra);
fp->l.upper = high >> 16;
fp->l.lower = low;
@@ -522,8 +522,8 @@ static int cpu_ld_floatx80_ra(CPUM68KState *env, uint32_t addr, FPReg *fp,
static int cpu_st_floatx80_ra(CPUM68KState *env, uint32_t addr, FPReg *fp,
uintptr_t ra)
{
- cpu_stl_data_ra(env, addr, fp->l.upper << 16, ra);
- cpu_stq_data_ra(env, addr + 4, fp->l.lower, ra);
+ cpu_stl_be_data_ra(env, addr, fp->l.upper << 16, ra);
+ cpu_stq_be_data_ra(env, addr + 4, fp->l.lower, ra);
return 12;
}
@@ -533,7 +533,7 @@ static int cpu_ld_float64_ra(CPUM68KState *env, uint32_t addr, FPReg *fp,
{
uint64_t val;
- val = cpu_ldq_data_ra(env, addr, ra);
+ val = cpu_ldq_be_data_ra(env, addr, ra);
fp->d = float64_to_floatx80(*(float64 *)&val, &env->fp_status);
return 8;
@@ -545,7 +545,7 @@ static int cpu_st_float64_ra(CPUM68KState *env, uint32_t addr, FPReg *fp,
float64 val;
val = floatx80_to_float64(fp->d, &env->fp_status);
- cpu_stq_data_ra(env, addr, *(uint64_t *)&val, ra);
+ cpu_stq_be_data_ra(env, addr, *(uint64_t *)&val, ra);
return 8;
}
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index e9c20a8e032..7139a8445d4 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -32,8 +32,8 @@ static void cf_rte(CPUM68KState *env)
uint32_t fmt;
sp = env->aregs[7];
- fmt = cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
- env->pc = cpu_ldl_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0);
+ fmt = cpu_ldl_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
+ env->pc = cpu_ldl_be_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0);
sp |= (fmt >> 28) & 3;
env->aregs[7] = sp + 8;
@@ -48,13 +48,13 @@ static void m68k_rte(CPUM68KState *env)
sp = env->aregs[7];
throwaway:
- sr = cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
+ sr = cpu_lduw_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
sp += 2;
- env->pc = cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
+ env->pc = cpu_ldl_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
sp += 4;
if (m68k_feature(env, M68K_FEATURE_EXCEPTION_FORMAT_VEC)) {
/* all except 68000 */
- fmt = cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
+ fmt = cpu_lduw_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
sp += 2;
switch (fmt >> 12) {
case 0:
@@ -250,12 +250,12 @@ static void cf_interrupt_all(CPUM68KState *env, int is_hw)
/* ??? This could cause MMU faults. */
sp &= ~3;
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, retaddr, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, retaddr, MMU_KERNEL_IDX, 0);
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, fmt, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, fmt, MMU_KERNEL_IDX, 0);
env->aregs[7] = sp;
/* Jump to vector. */
- env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
+ env->pc = cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
do_plugin_vcpu_interrupt_cb(cs, retaddr);
}
@@ -270,24 +270,25 @@ static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp,
switch (format) {
case 4:
*sp -= 4;
- cpu_stl_mmuidx_ra(env, *sp, env->pc, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, *sp, env->pc, MMU_KERNEL_IDX, 0);
*sp -= 4;
- cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);
break;
case 3:
case 2:
*sp -= 4;
- cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);
break;
}
*sp -= 2;
- cpu_stw_mmuidx_ra(env, *sp, (format << 12) + (cs->exception_index << 2),
- MMU_KERNEL_IDX, 0);
+ cpu_stw_be_mmuidx_ra(env, *sp,
+ (format << 12) + (cs->exception_index << 2),
+ MMU_KERNEL_IDX, 0);
}
*sp -= 4;
- cpu_stl_mmuidx_ra(env, *sp, retaddr, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, *sp, retaddr, MMU_KERNEL_IDX, 0);
*sp -= 2;
- cpu_stw_mmuidx_ra(env, *sp, sr, MMU_KERNEL_IDX, 0);
+ cpu_stw_be_mmuidx_ra(env, *sp, sr, MMU_KERNEL_IDX, 0);
}
static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
@@ -346,49 +347,49 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
env->mmu.fault = true;
/* push data 3 */
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* push data 2 */
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* push data 1 */
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 1 / push data 0 */
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 1 address */
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 2 data */
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 2 address */
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 3 data */
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 3 address */
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
/* fault address */
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
/* write back 1 status */
sp -= 2;
- cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 2 status */
sp -= 2;
- cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* write back 3 status */
sp -= 2;
- cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
+ cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
/* special status word */
sp -= 2;
- cpu_stw_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);
+ cpu_stw_be_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);
/* effective address */
sp -= 4;
- cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
+ cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
do_stack_frame(env, &sp, 7, oldsr, 0, env->pc);
env->mmu.fault = false;
@@ -436,7 +437,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
env->aregs[7] = sp;
/* Jump to vector. */
- env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
+ env->pc = cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
do_plugin_vcpu_interrupt_cb(cs, last_pc);
}
@@ -784,11 +785,11 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
int16_t l1, l2;
uintptr_t ra = GETPC();
- l1 = cpu_lduw_data_ra(env, a1, ra);
- l2 = cpu_lduw_data_ra(env, a2, ra);
+ l1 = cpu_lduw_be_data_ra(env, a1, ra);
+ l2 = cpu_lduw_be_data_ra(env, a2, ra);
if (l1 == c1 && l2 == c2) {
- cpu_stw_data_ra(env, a1, u1, ra);
- cpu_stw_data_ra(env, a2, u2, ra);
+ cpu_stw_be_data_ra(env, a1, u1, ra);
+ cpu_stw_be_data_ra(env, a2, u2, ra);
}
if (c1 != l1) {
@@ -845,11 +846,11 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2,
}
} else {
/* We're executing in a serial context -- no need to be atomic. */
- l1 = cpu_ldl_data_ra(env, a1, ra);
- l2 = cpu_ldl_data_ra(env, a2, ra);
+ l1 = cpu_ldl_be_data_ra(env, a1, ra);
+ l2 = cpu_ldl_be_data_ra(env, a2, ra);
if (l1 == c1 && l2 == c2) {
- cpu_stl_data_ra(env, a1, u1, ra);
- cpu_stl_data_ra(env, a2, u2, ra);
+ cpu_stl_be_data_ra(env, a1, u1, ra);
+ cpu_stl_be_data_ra(env, a2, u2, ra);
}
}
@@ -951,12 +952,12 @@ static uint64_t bf_load(CPUM68KState *env, uint32_t addr, int blen,
case 0:
return cpu_ldub_data_ra(env, addr, ra);
case 1:
- return cpu_lduw_data_ra(env, addr, ra);
+ return cpu_lduw_be_data_ra(env, addr, ra);
case 2:
case 3:
- return cpu_ldl_data_ra(env, addr, ra);
+ return cpu_ldl_be_data_ra(env, addr, ra);
case 4:
- return cpu_ldq_data_ra(env, addr, ra);
+ return cpu_ldq_be_data_ra(env, addr, ra);
default:
g_assert_not_reached();
}
@@ -970,14 +971,14 @@ static void bf_store(CPUM68KState *env, uint32_t addr, int blen,
cpu_stb_data_ra(env, addr, data, ra);
break;
case 1:
- cpu_stw_data_ra(env, addr, data, ra);
+ cpu_stw_be_data_ra(env, addr, data, ra);
break;
case 2:
case 3:
- cpu_stl_data_ra(env, addr, data, ra);
+ cpu_stl_be_data_ra(env, addr, data, ra);
break;
case 4:
- cpu_stq_data_ra(env, addr, data, ra);
+ cpu_stq_be_data_ra(env, addr, data, ra);
break;
default:
g_assert_not_reached();
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 08/22] target/s390x: Use big-endian variant of cpu_ld/st_data*()
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 07/22] target/m68k: " Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 09/22] target/sparc: " Philippe Mathieu-Daudé
` (13 subsequent siblings)
21 siblings, 0 replies; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Thomas Huth, Ilya Leoshkevich,
David Hildenbrand
We only build the S390x target using big endianness order,
therefore the cpu_ld/st_data*() definitions expand to the
big endian declarations. Use the explicit big-endian variants.
Mechanical change running:
$ tgt=s390x; \
end=be; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
target/s390x/tcg/mem_helper.c | 48 +++++++++++++++++------------------
target/s390x/tcg/vec_helper.c | 8 +++---
2 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 24675fc818d..482c3febf91 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -101,7 +101,7 @@ static inline uint64_t cpu_ldusize_data_ra(CPUS390XState *env, uint64_t addr,
case 1:
return cpu_ldub_data_ra(env, addr, ra);
case 2:
- return cpu_lduw_data_ra(env, addr, ra);
+ return cpu_lduw_be_data_ra(env, addr, ra);
default:
abort();
}
@@ -117,7 +117,7 @@ static inline void cpu_stsize_data_ra(CPUS390XState *env, uint64_t addr,
cpu_stb_data_ra(env, addr, value, ra);
break;
case 2:
- cpu_stw_data_ra(env, addr, value, ra);
+ cpu_stw_be_data_ra(env, addr, value, ra);
break;
default:
abort();
@@ -865,7 +865,7 @@ void HELPER(srstu)(CPUS390XState *env, uint32_t r1, uint32_t r2)
env->cc_op = 2;
return;
}
- v = cpu_lduw_data_ra(env, str + len, ra);
+ v = cpu_lduw_be_data_ra(env, str + len, ra);
if (v == c) {
/* Character found. Set R1 to the location; R2 is unmodified. */
env->cc_op = 1;
@@ -1022,7 +1022,7 @@ void HELPER(lam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
for (i = r1;; i = (i + 1) % 16) {
- env->aregs[i] = cpu_ldl_data_ra(env, a2, ra);
+ env->aregs[i] = cpu_ldl_be_data_ra(env, a2, ra);
a2 += 4;
if (i == r3) {
@@ -1042,7 +1042,7 @@ void HELPER(stam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
for (i = r1;; i = (i + 1) % 16) {
- cpu_stl_data_ra(env, a2, env->aregs[i], ra);
+ cpu_stl_be_data_ra(env, a2, env->aregs[i], ra);
a2 += 4;
if (i == r3) {
@@ -1363,7 +1363,7 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1,
/* Process full words as available. */
for (len = 0; len + 4 <= max_len; len += 4, src += 4) {
- cksm += (uint32_t)cpu_ldl_data_ra(env, src, ra);
+ cksm += (uint32_t)cpu_ldl_be_data_ra(env, src, ra);
}
switch (max_len - len) {
@@ -1372,11 +1372,11 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1,
len += 1;
break;
case 2:
- cksm += cpu_lduw_data_ra(env, src, ra) << 16;
+ cksm += cpu_lduw_be_data_ra(env, src, ra) << 16;
len += 2;
break;
case 3:
- cksm += cpu_lduw_data_ra(env, src, ra) << 16;
+ cksm += cpu_lduw_be_data_ra(env, src, ra) << 16;
cksm += cpu_ldub_data_ra(env, src + 2, ra) << 8;
len += 3;
break;
@@ -1955,7 +1955,7 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
for (i = r1;; i = (i + 1) % 16) {
- uint64_t val = cpu_ldq_data_ra(env, src, ra);
+ uint64_t val = cpu_ldq_be_data_ra(env, src, ra);
if (env->cregs[i] != val && i >= 9 && i <= 11) {
PERchanged = true;
}
@@ -1992,7 +1992,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
for (i = r1;; i = (i + 1) % 16) {
- uint32_t val = cpu_ldl_data_ra(env, src, ra);
+ uint32_t val = cpu_ldl_be_data_ra(env, src, ra);
uint64_t val64 = deposit64(env->cregs[i], 0, 32, val);
if ((uint32_t)env->cregs[i] != val && i >= 9 && i <= 11) {
PERchanged = true;
@@ -2028,7 +2028,7 @@ void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
for (i = r1;; i = (i + 1) % 16) {
- cpu_stq_data_ra(env, dest, env->cregs[i], ra);
+ cpu_stq_be_data_ra(env, dest, env->cregs[i], ra);
dest += sizeof(uint64_t);
if (i == r3) {
@@ -2048,7 +2048,7 @@ void HELPER(stctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
for (i = r1;; i = (i + 1) % 16) {
- cpu_stl_data_ra(env, dest, env->cregs[i], ra);
+ cpu_stl_be_data_ra(env, dest, env->cregs[i], ra);
dest += sizeof(uint32_t);
if (i == r3) {
@@ -2065,7 +2065,7 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64_t real_addr)
real_addr = wrap_address(env, real_addr) & TARGET_PAGE_MASK;
for (i = 0; i < TARGET_PAGE_SIZE; i += 8) {
- cpu_stq_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra);
+ cpu_stq_be_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra);
}
return 0;
@@ -2324,11 +2324,11 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4)
for (i = 0; i < entries; i++) {
/* addresses are not wrapped in 24/31bit mode but table index is */
raddr = table + ((index + i) & 0x7ff) * sizeof(entry);
- entry = cpu_ldq_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra);
+ entry = cpu_ldq_be_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra);
if (!(entry & REGION_ENTRY_I)) {
/* we are allowed to not store if already invalid */
entry |= REGION_ENTRY_I;
- cpu_stq_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra);
+ cpu_stq_be_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra);
}
}
}
@@ -2355,9 +2355,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
pte_addr += VADDR_PAGE_TX(vaddr) * 8;
/* Mark the page table entry as invalid */
- pte = cpu_ldq_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra);
+ pte = cpu_ldq_be_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra);
pte |= PAGE_ENTRY_I;
- cpu_stq_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra);
+ cpu_stq_be_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra);
/* XXX we exploit the fact that Linux passes the exact virtual
address here - it's not obliged to! */
@@ -2695,7 +2695,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen,
if (ilen < 2) {
return 0;
}
- s0 = cpu_lduw_data_ra(env, addr, ra);
+ s0 = cpu_lduw_be_data_ra(env, addr, ra);
if ((s0 & 0xfc00) != 0xd800) {
/* one word character */
l = 2;
@@ -2706,7 +2706,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen,
if (ilen < 4) {
return 0;
}
- s1 = cpu_lduw_data_ra(env, addr + 2, ra);
+ s1 = cpu_lduw_be_data_ra(env, addr + 2, ra);
c = extract32(s0, 6, 4) + 1;
c = (c << 6) | (s0 & 0x3f);
c = (c << 10) | (s1 & 0x3ff);
@@ -2730,7 +2730,7 @@ static int decode_utf32(CPUS390XState *env, uint64_t addr, uint64_t ilen,
if (ilen < 4) {
return 0;
}
- c = cpu_ldl_data_ra(env, addr, ra);
+ c = cpu_ldl_be_data_ra(env, addr, ra);
if ((c >= 0xd800 && c <= 0xdbff) || c > 0x10ffff) {
/* invalid unicode character */
return 2;
@@ -2792,7 +2792,7 @@ static int encode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen,
if (ilen < 2) {
return 1;
}
- cpu_stw_data_ra(env, addr, c, ra);
+ cpu_stw_be_data_ra(env, addr, c, ra);
*olen = 2;
} else {
/* two word character */
@@ -2802,8 +2802,8 @@ static int encode_utf16(CPUS390XState *env, uint64_t addr, uint64_t ilen,
d1 = 0xdc00 | extract32(c, 0, 10);
d0 = 0xd800 | extract32(c, 10, 6);
d0 = deposit32(d0, 6, 4, extract32(c, 16, 5) - 1);
- cpu_stw_data_ra(env, addr + 0, d0, ra);
- cpu_stw_data_ra(env, addr + 2, d1, ra);
+ cpu_stw_be_data_ra(env, addr + 0, d0, ra);
+ cpu_stw_be_data_ra(env, addr + 2, d1, ra);
*olen = 4;
}
@@ -2816,7 +2816,7 @@ static int encode_utf32(CPUS390XState *env, uint64_t addr, uint64_t ilen,
if (ilen < 4) {
return 1;
}
- cpu_stl_data_ra(env, addr, c, ra);
+ cpu_stl_be_data_ra(env, addr, c, ra);
*olen = 4;
return -1;
}
diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c
index 46ec4a947dd..304745c971b 100644
--- a/target/s390x/tcg/vec_helper.c
+++ b/target/s390x/tcg/vec_helper.c
@@ -45,9 +45,9 @@ void HELPER(vll)(CPUS390XState *env, void *v1, uint64_t addr, uint64_t bytes)
if (likely(bytes >= 16)) {
uint64_t t0, t1;
- t0 = cpu_ldq_data_ra(env, addr, GETPC());
+ t0 = cpu_ldq_be_data_ra(env, addr, GETPC());
addr = wrap_address(env, addr + 8);
- t1 = cpu_ldq_data_ra(env, addr, GETPC());
+ t1 = cpu_ldq_be_data_ra(env, addr, GETPC());
s390_vec_write_element64(v1, 0, t0);
s390_vec_write_element64(v1, 1, t1);
} else {
@@ -195,9 +195,9 @@ void HELPER(vstl)(CPUS390XState *env, const void *v1, uint64_t addr,
probe_write_access(env, addr, MIN(bytes, 16), GETPC());
if (likely(bytes >= 16)) {
- cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETPC());
+ cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETPC());
addr = wrap_address(env, addr + 8);
- cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETPC());
+ cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETPC());
} else {
int i;
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 09/22] target/sparc: Use big-endian variant of cpu_ld/st_data*()
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 08/22] target/s390x: " Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 10/22] target/sh4: Replace cpu_stl_data() call in OCBI helper Philippe Mathieu-Daudé
` (12 subsequent siblings)
21 siblings, 0 replies; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Mark Cave-Ayland, Artyom Tarasenko
We only build the SPARC targets using big endianness order,
therefore the cpu_ld/st_data*() definitions expand to the big
endian declarations. Use the explicit big-endian variants.
Mechanical change running:
$ tgt=sparc; \
end=be; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/ldst_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 2c63eb9e036..bd0257d313a 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -1228,13 +1228,13 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
ret = cpu_ldub_data(env, addr);
break;
case 2:
- ret = cpu_lduw_data(env, addr);
+ ret = cpu_lduw_be_data(env, addr);
break;
case 4:
- ret = cpu_ldl_data(env, addr);
+ ret = cpu_ldl_be_data(env, addr);
break;
case 8:
- ret = cpu_ldq_data(env, addr);
+ ret = cpu_ldq_be_data(env, addr);
break;
default:
g_assert_not_reached();
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 10/22] target/sh4: Replace cpu_stl_data() call in OCBI helper
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 09/22] target/sparc: " Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-05 20:03 ` Richard Henderson
2025-12-05 20:06 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 11/22] target/mips: Use big-endian variant of cpu_ld/st_data*() for MSA opcode Philippe Mathieu-Daudé
` (11 subsequent siblings)
21 siblings, 2 replies; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Yoshinori Sato
In preparation of removing the cpu_stl_data() call,
inline it. Set the return address argument.
See commit 852d481faf7 ("SH: Improve movca.l/ocbi
emulation") for more context on this code.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/sh4/op_helper.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 557b1bf4972..669bc84cb64 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -136,6 +136,8 @@ void helper_discard_movcal_backup(CPUSH4State *env)
void helper_ocbi(CPUSH4State *env, uint32_t address)
{
+ unsigned mmu_idx = cpu_mmu_index(env_cpu(env), false);
+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_UNALN, mmu_idx);
memory_content **current = &(env->movcal_backup);
while (*current)
{
@@ -143,7 +145,8 @@ void helper_ocbi(CPUSH4State *env, uint32_t address)
if ((a & ~0x1F) == (address & ~0x1F))
{
memory_content *next = (*current)->next;
- cpu_stl_data(env, a, (*current)->value);
+
+ cpu_stl_mmu(env, a, (*current)->value, oi, GETPC());
if (next == NULL)
{
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 11/22] target/mips: Use big-endian variant of cpu_ld/st_data*() for MSA opcode
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 10/22] target/sh4: Replace cpu_stl_data() call in OCBI helper Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-12 16:28 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 12/22] target/mips: Introduce loadu8() & loads4() helpers Philippe Mathieu-Daudé
` (10 subsequent siblings)
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
MSA vectors are accessed in big endianness.
Per the "MIPS® SIMD Architecture" (MD00926 rev 1.03):
3.1 Registers Layout
MSA vectors are stored in memory starting from the 0th element at
the lowest byte address. The byte order of each element follows the
big- or little-endian convention of the system configuration.
Use the explicit big-endian variants of cpu_ld/st_data*().
Running files in tests/tcg/mips/user/ase/msa shows:
NLOC.B | PASS: 80 | FAIL: 0 | elapsed time: 0.21 ms |
NLOC.H | PASS: 80 | FAIL: 0 | elapsed time: 0.22 ms |
NLOC.W | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms |
NLOC.D | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms |
NLZC.B | PASS: 80 | FAIL: 0 | elapsed time: 0.19 ms |
NLZC.H | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms |
NLZC.W | PASS: 80 | FAIL: 0 | elapsed time: 0.21 ms |
NLZC.D | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms |
PCNT.B | PASS: 80 | FAIL: 0 | elapsed time: 0.17 ms |
PCNT.H | PASS: 80 | FAIL: 0 | elapsed time: 0.19 ms |
PCNT.W | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms |
PCNT.D | PASS: 80 | FAIL: 0 | elapsed time: 0.19 ms |
BINSL.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
BINSL.H | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
BINSL.W | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
BINSL.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
BINSR.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
BINSR.H | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms |
BINSR.W | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms |
BINSR.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
BMNZ.V | PASS: 112 | FAIL: 0 | elapsed time: 0.65 ms |
BMZ.V | PASS: 112 | FAIL: 0 | elapsed time: 0.59 ms |
BSEL.V | PASS: 112 | FAIL: 0 | elapsed time: 0.60 ms |
BCLR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
BCLR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
BCLR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
BCLR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
BNEG.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
BNEG.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
BNEG.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
BNEG.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
BSET.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
BSET.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
BSET.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
BSET.D | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms |
MADD_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.60 ms |
MADD_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.83 ms |
MADDR_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.62 ms |
MADDR_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
MSUB_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
MSUB_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
MSUBR_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
MSUBR_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
MUL_Q.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MUL_Q.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MULR_Q.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MULR_Q.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
FMAX_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.36 ms |
FMAX_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms |
FMAX.W | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms |
FMAX.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms |
FMIN_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.36 ms |
FMIN_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms |
FMIN.W | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms |
FMIN.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
ADD_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADD_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADD_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADD_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
ADDS_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
ADDS_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms |
ADDS_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADDS_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADDS_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADDS_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADDS_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.80 ms |
ADDS_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
ADDS_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADDS_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADDS_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADDS_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADDV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
ADDV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ADDV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
ADDV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
HADD_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
HADD_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
HADD_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
HADD_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
HADD_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms |
HADD_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVE_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVE_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVE_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVE_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVE_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVE_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVE_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
AVE_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVER_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVER_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
AVER_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVER_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVER_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
AVER_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVER_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AVER_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
CEQ.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
CEQ.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
CEQ.W | PASS: 80 | FAIL: 0 | elapsed time: 0.38 ms |
CEQ.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
CLE_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
CLE_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
CLE_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
CLE_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
CLE_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
CLE_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
CLE_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms |
CLE_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
CLT_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms |
CLT_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
CLT_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
CLT_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
CLT_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
CLT_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms |
CLT_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
CLT_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
DIV_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
DIV_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
DIV_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
DIV_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
DIV_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.39 ms |
DIV_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
DIV_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
DIV_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
DOTP_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
DOTP_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms |
DOTP_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
DOTP_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
DOTP_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms |
DOTP_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
DPADD_S.H | PASS: 112 | FAIL: 0 | elapsed time: 0.59 ms |
DPADD_S.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
DPADD_S.D | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms |
DPADD_U.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
DPADD_U.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
DPADD_U.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
DPSUB_S.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
DPSUB_S.W | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
DPSUB_S.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
DPSUB_U.H | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms |
DPSUB_U.W | PASS: 112 | FAIL: 0 | elapsed time: 0.59 ms |
DPSUB_U.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
MAX_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MAX_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
MAX_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms |
MAX_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MAX_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MAX_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MAX_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MAX_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms |
MAX_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms |
MAX_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MAX_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
MAX_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MIN_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
MIN_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MIN_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MIN_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MIN_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MIN_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms |
MIN_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MIN_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MIN_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
MIN_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MIN_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MIN_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
MOD_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
MOD_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
MOD_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MOD_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MOD_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.37 ms |
MOD_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
MOD_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MOD_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MADDV.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
MADDV.H | PASS: 112 | FAIL: 0 | elapsed time: 0.63 ms |
MADDV.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
MADDV.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
MSUBV.B | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
MSUBV.H | PASS: 112 | FAIL: 0 | elapsed time: 0.65 ms |
MSUBV.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
MSUBV.D | PASS: 112 | FAIL: 0 | elapsed time: 0.65 ms |
MULV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
MULV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MULV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
MULV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ASUB_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ASUB_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ASUB_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ASUB_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ASUB_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.44 ms |
ASUB_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
ASUB_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ASUB_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
HSUB_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
HSUB_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
HSUB_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
HSUB_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
HSUB_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
HSUB_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
SUBS_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
SUBS_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.38 ms |
SUBS_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
SUBS_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBS_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBS_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms |
SUBS_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
SUBS_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBSUS_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBSUS_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
SUBSUS_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBSUS_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBSUU_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBSUU_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
SUBSUU_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBSUU_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SUBV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ILVEV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms |
ILVEV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
ILVEV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
ILVEV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms |
ILVOD.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ILVOD.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ILVOD.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ILVOD.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ILVL.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
ILVL.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ILVL.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ILVL.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ILVR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ILVR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
ILVR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
ILVR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
AND.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
NOR.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
OR.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
XOR.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
MOVE.V | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms |
PCKEV.B | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
PCKEV.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms |
PCKEV.W | PASS: 112 | FAIL: 0 | elapsed time: 0.68 ms |
PCKEV.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
PCKOD.B | PASS: 112 | FAIL: 0 | elapsed time: 0.61 ms |
PCKOD.H | PASS: 112 | FAIL: 0 | elapsed time: 0.62 ms |
PCKOD.W | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms |
PCKOD.D | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms |
VSHF.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
VSHF.H | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
VSHF.W | PASS: 112 | FAIL: 0 | elapsed time: 0.62 ms |
VSHF.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms |
SLL.B | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms |
SLL.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SLL.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SLL.D | PASS: 80 | FAIL: 0 | elapsed time: 0.38 ms |
SRA.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
SRA.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
SRA.W | PASS: 80 | FAIL: 0 | elapsed time: 0.37 ms |
SRA.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SRAR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
SRAR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
SRAR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
SRAR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SRL.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SRL.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms |
SRL.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SRL.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SRLR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
SRLR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms |
SRLR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms |
SRLR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms |
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/msa_helper.c | 51 ++++++++++++++++++++++--------------
1 file changed, 31 insertions(+), 20 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index f554b3d10ee..d6ce17abf9a 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -8231,8 +8231,8 @@ void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
uint64_t d0, d1;
/* Load 8 bytes at a time. Vector element ordering makes this LE. */
- d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);
- d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);
+ d0 = cpu_ldq_be_data_ra(env, addr + 0, ra);
+ d1 = cpu_ldq_be_data_ra(env, addr + 8, ra);
pwd->d[0] = d0;
pwd->d[1] = d1;
}
@@ -8248,9 +8248,9 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
* Load 8 bytes at a time. Use little-endian load, then for
* big-endian target, we must then swap the four halfwords.
*/
- d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);
- d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);
- if (mips_env_is_bigendian(env)) {
+ d0 = cpu_ldq_be_data_ra(env, addr + 0, ra);
+ d1 = cpu_ldq_be_data_ra(env, addr + 8, ra);
+ if (!mips_env_is_bigendian(env)) {
d0 = bswap16x4(d0);
d1 = bswap16x4(d1);
}
@@ -8269,9 +8269,9 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
* Load 8 bytes at a time. Use little-endian load, then for
* big-endian target, we must then bswap the two words.
*/
- d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);
- d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);
- if (mips_env_is_bigendian(env)) {
+ d0 = cpu_ldq_be_data_ra(env, addr + 0, ra);
+ d1 = cpu_ldq_be_data_ra(env, addr + 8, ra);
+ if (!mips_env_is_bigendian(env)) {
d0 = bswap32x2(d0);
d1 = bswap32x2(d1);
}
@@ -8286,8 +8286,12 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
uintptr_t ra = GETPC();
uint64_t d0, d1;
- d0 = cpu_ldq_data_ra(env, addr + 0, ra);
- d1 = cpu_ldq_data_ra(env, addr + 8, ra);
+ d0 = cpu_ldq_be_data_ra(env, addr + 0, ra);
+ d1 = cpu_ldq_be_data_ra(env, addr + 8, ra);
+ if (!mips_env_is_bigendian(env)) {
+ d0 = bswap64(d0);
+ d1 = bswap64(d1);
+ }
pwd->d[0] = d0;
pwd->d[1] = d1;
}
@@ -8320,8 +8324,8 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
ensure_writable_pages(env, addr, mmu_idx, ra);
/* Store 8 bytes at a time. Vector element ordering makes this LE. */
- cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra);
- cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra);
+ cpu_stq_be_data_ra(env, addr + 0, pwd->d[0], ra);
+ cpu_stq_be_data_ra(env, addr + 8, pwd->d[1], ra);
}
void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
@@ -8337,12 +8341,12 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
/* Store 8 bytes at a time. See helper_msa_ld_h. */
d0 = pwd->d[0];
d1 = pwd->d[1];
- if (mips_env_is_bigendian(env)) {
+ if (!mips_env_is_bigendian(env)) {
d0 = bswap16x4(d0);
d1 = bswap16x4(d1);
}
- cpu_stq_le_data_ra(env, addr + 0, d0, ra);
- cpu_stq_le_data_ra(env, addr + 8, d1, ra);
+ cpu_stq_be_data_ra(env, addr + 0, d0, ra);
+ cpu_stq_be_data_ra(env, addr + 8, d1, ra);
}
void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
@@ -8358,12 +8362,12 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
/* Store 8 bytes at a time. See helper_msa_ld_w. */
d0 = pwd->d[0];
d1 = pwd->d[1];
- if (mips_env_is_bigendian(env)) {
+ if (!mips_env_is_bigendian(env)) {
d0 = bswap32x2(d0);
d1 = bswap32x2(d1);
}
- cpu_stq_le_data_ra(env, addr + 0, d0, ra);
- cpu_stq_le_data_ra(env, addr + 8, d1, ra);
+ cpu_stq_be_data_ra(env, addr + 0, d0, ra);
+ cpu_stq_be_data_ra(env, addr + 8, d1, ra);
}
void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
@@ -8372,9 +8376,16 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
int mmu_idx = mips_env_mmu_index(env);
uintptr_t ra = GETPC();
+ uint64_t d0, d1;
ensure_writable_pages(env, addr, mmu_idx, GETPC());
- cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra);
- cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra);
+ d0 = pwd->d[0];
+ d1 = pwd->d[1];
+ if (!mips_env_is_bigendian(env)) {
+ d0 = bswap64(d0);
+ d1 = bswap64(d1);
+ }
+ cpu_stq_be_data_ra(env, addr + 0, d0, ra);
+ cpu_stq_be_data_ra(env, addr + 8, d1, ra);
}
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 12/22] target/mips: Introduce loadu8() & loads4() helpers
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 11/22] target/mips: Use big-endian variant of cpu_ld/st_data*() for MSA opcode Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-12 16:32 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 13/22] target/mips: Pass MemOpIdx to atomic load helpers Philippe Mathieu-Daudé
` (9 subsequent siblings)
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
Rather than using complex cast via macro, introduce a pair
of helpers doing explicit casting.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/ldst_helper.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
index 10319bf03a6..c1c4a60cf3f 100644
--- a/target/mips/tcg/ldst_helper.c
+++ b/target/mips/tcg/ldst_helper.c
@@ -29,7 +29,7 @@
#ifndef CONFIG_USER_ONLY
-#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
+#define HELPER_LD_ATOMIC(name, almask, cpu_load) \
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
{ \
if (arg & almask) { \
@@ -41,12 +41,23 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
env->CP0_LLAddr = cpu_mips_translate_address(env, arg, MMU_DATA_LOAD, \
GETPC()); \
env->lladdr = arg; \
- env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
+ env->llval = cpu_load(env, arg, mem_idx, GETPC()); \
return env->llval; \
}
-HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t))
+
+static target_ulong loads4(CPUMIPSState *env, target_ulong arg,
+ unsigned mem_idx, uintptr_t ra)
+{
+ return (target_long)(int32_t)cpu_ldl_mmuidx_ra(env, arg, mem_idx, ra);
+}
+HELPER_LD_ATOMIC(ll, 0x3, loads4)
#ifdef TARGET_MIPS64
-HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
+static target_ulong loadu8(CPUMIPSState *env, target_ulong arg,
+ unsigned mem_idx, uintptr_t ra)
+{
+ return (target_ulong)cpu_ldq_mmuidx_ra(env, arg, mem_idx, ra);
+}
+HELPER_LD_ATOMIC(lld, 0x7, loadu8)
#endif
#undef HELPER_LD_ATOMIC
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 13/22] target/mips: Pass MemOpIdx to atomic load helpers
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 12/22] target/mips: Introduce loadu8() & loads4() helpers Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-12 16:33 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 14/22] target/mips: Drop almask argument of HELPER_LD_ATOMIC() macro Philippe Mathieu-Daudé
` (8 subsequent siblings)
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
Pass a full MemOpIdx at translation, then recover the
MMU index calling get_mmuidx() in the helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/ldst_helper.c | 4 +++-
target/mips/tcg/translate.c | 9 +++++----
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
index c1c4a60cf3f..013cd825dac 100644
--- a/target/mips/tcg/ldst_helper.c
+++ b/target/mips/tcg/ldst_helper.c
@@ -30,8 +30,10 @@
#ifndef CONFIG_USER_ONLY
#define HELPER_LD_ATOMIC(name, almask, cpu_load) \
-target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
+target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int memop_idx)\
{ \
+ MemOpIdx oi = memop_idx; \
+ unsigned mem_idx = get_mmuidx(oi); \
if (arg & almask) { \
if (!(env->hflags & MIPS_HFLAG_DM)) { \
env->CP0_BadVAddr = arg; \
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 54849e9ff1a..c476271d6d5 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1932,16 +1932,17 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); \
}
#else
-#define OP_LD_ATOMIC(insn, ignored_memop) \
+#define OP_LD_ATOMIC(insn, mop) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
DisasContext *ctx) \
{ \
- gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \
+ MemOpIdx oi = make_memop_idx(mop | mo_endian(ctx), mem_idx); \
+ gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(oi)); \
}
#endif
-OP_LD_ATOMIC(ll, mo_endian(ctx) | MO_SL);
+OP_LD_ATOMIC(ll, MO_SL);
#if defined(TARGET_MIPS64)
-OP_LD_ATOMIC(lld, mo_endian(ctx) | MO_UQ);
+OP_LD_ATOMIC(lld, MO_UQ);
#endif
#undef OP_LD_ATOMIC
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 14/22] target/mips: Drop almask argument of HELPER_LD_ATOMIC() macro
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 13/22] target/mips: Pass MemOpIdx to atomic load helpers Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-12 16:35 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 15/22] target/mips: Inline cpu_ld*_mmuidx_ra() calls in atomic load helpers Philippe Mathieu-Daudé
` (7 subsequent siblings)
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
HELPER_LD_ATOMIC() now has a MemOpIdx, from which we
can extract the MemOp size. Use it to check the address
alignment.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/ldst_helper.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
index 013cd825dac..bef384575c2 100644
--- a/target/mips/tcg/ldst_helper.c
+++ b/target/mips/tcg/ldst_helper.c
@@ -29,12 +29,14 @@
#ifndef CONFIG_USER_ONLY
-#define HELPER_LD_ATOMIC(name, almask, cpu_load) \
+#define HELPER_LD_ATOMIC(name, cpu_load) \
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int memop_idx)\
{ \
MemOpIdx oi = memop_idx; \
unsigned mem_idx = get_mmuidx(oi); \
- if (arg & almask) { \
+ MemOp op = get_memop(oi); \
+ unsigned size = memop_size(op); \
+ if (arg & (size - 1)) { \
if (!(env->hflags & MIPS_HFLAG_DM)) { \
env->CP0_BadVAddr = arg; \
} \
@@ -52,14 +54,14 @@ static target_ulong loads4(CPUMIPSState *env, target_ulong arg,
{
return (target_long)(int32_t)cpu_ldl_mmuidx_ra(env, arg, mem_idx, ra);
}
-HELPER_LD_ATOMIC(ll, 0x3, loads4)
+HELPER_LD_ATOMIC(ll, loads4)
#ifdef TARGET_MIPS64
static target_ulong loadu8(CPUMIPSState *env, target_ulong arg,
unsigned mem_idx, uintptr_t ra)
{
return (target_ulong)cpu_ldq_mmuidx_ra(env, arg, mem_idx, ra);
}
-HELPER_LD_ATOMIC(lld, 0x7, loadu8)
+HELPER_LD_ATOMIC(lld, loadu8)
#endif
#undef HELPER_LD_ATOMIC
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 15/22] target/mips: Inline cpu_ld*_mmuidx_ra() calls in atomic load helpers
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 14/22] target/mips: Drop almask argument of HELPER_LD_ATOMIC() macro Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 16/22] target/mips: Expand HELPER_LD_ATOMIC() Philippe Mathieu-Daudé
` (6 subsequent siblings)
21 siblings, 0 replies; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
In preparation of removing the cpu_ld*_mmuidx_ra() calls, inline them.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/ldst_helper.c | 11 +++++------
target/mips/tcg/translate.c | 2 +-
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
index bef384575c2..85f73c9081d 100644
--- a/target/mips/tcg/ldst_helper.c
+++ b/target/mips/tcg/ldst_helper.c
@@ -33,7 +33,6 @@
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int memop_idx)\
{ \
MemOpIdx oi = memop_idx; \
- unsigned mem_idx = get_mmuidx(oi); \
MemOp op = get_memop(oi); \
unsigned size = memop_size(op); \
if (arg & (size - 1)) { \
@@ -45,21 +44,21 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int memop_idx)\
env->CP0_LLAddr = cpu_mips_translate_address(env, arg, MMU_DATA_LOAD, \
GETPC()); \
env->lladdr = arg; \
- env->llval = cpu_load(env, arg, mem_idx, GETPC()); \
+ env->llval = cpu_load(env, arg, oi, GETPC()); \
return env->llval; \
}
static target_ulong loads4(CPUMIPSState *env, target_ulong arg,
- unsigned mem_idx, uintptr_t ra)
+ MemOpIdx oi, uintptr_t ra)
{
- return (target_long)(int32_t)cpu_ldl_mmuidx_ra(env, arg, mem_idx, ra);
+ return (target_long)(int32_t)cpu_ldl_mmu(env, arg, oi, ra);
}
HELPER_LD_ATOMIC(ll, loads4)
#ifdef TARGET_MIPS64
static target_ulong loadu8(CPUMIPSState *env, target_ulong arg,
- unsigned mem_idx, uintptr_t ra)
+ MemOpIdx oi, uintptr_t ra)
{
- return (target_ulong)cpu_ldq_mmuidx_ra(env, arg, mem_idx, ra);
+ return (target_ulong)cpu_ldq_mmu(env, arg, oi, ra);
}
HELPER_LD_ATOMIC(lld, loadu8)
#endif
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index c476271d6d5..bb9e91069d6 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1936,7 +1936,7 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
DisasContext *ctx) \
{ \
- MemOpIdx oi = make_memop_idx(mop | mo_endian(ctx), mem_idx); \
+ MemOpIdx oi = make_memop_idx(mop | mo_endian(ctx) | MO_UNALN, mem_idx);\
gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(oi)); \
}
#endif
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 16/22] target/mips: Expand HELPER_LD_ATOMIC()
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 15/22] target/mips: Inline cpu_ld*_mmuidx_ra() calls in atomic load helpers Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-12 16:46 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 17/22] target/mips: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers Philippe Mathieu-Daudé
` (5 subsequent siblings)
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
Since it is easier to maintain a plain C function,
expand the HELPER_LD_ATOMIC() macro as do_ll().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/ldst_helper.c | 51 +++++++++++++++++++++--------------
1 file changed, 31 insertions(+), 20 deletions(-)
diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
index 85f73c9081d..f3652034afa 100644
--- a/target/mips/tcg/ldst_helper.c
+++ b/target/mips/tcg/ldst_helper.c
@@ -29,23 +29,26 @@
#ifndef CONFIG_USER_ONLY
-#define HELPER_LD_ATOMIC(name, cpu_load) \
-target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int memop_idx)\
-{ \
- MemOpIdx oi = memop_idx; \
- MemOp op = get_memop(oi); \
- unsigned size = memop_size(op); \
- if (arg & (size - 1)) { \
- if (!(env->hflags & MIPS_HFLAG_DM)) { \
- env->CP0_BadVAddr = arg; \
- } \
- do_raise_exception(env, EXCP_AdEL, GETPC()); \
- } \
- env->CP0_LLAddr = cpu_mips_translate_address(env, arg, MMU_DATA_LOAD, \
- GETPC()); \
- env->lladdr = arg; \
- env->llval = cpu_load(env, arg, oi, GETPC()); \
- return env->llval; \
+static target_ulong do_ll(target_ulong (*cpu_load_mmu)(CPUMIPSState *,
+ target_ulong,
+ MemOpIdx, uintptr_t),
+ CPUMIPSState *env, target_ulong arg,
+ MemOpIdx oi, uintptr_t ra)
+{
+ MemOp op = get_memop(oi);
+ unsigned size = memop_size(op);
+
+ if (arg & (size - 1)) {
+ if (!(env->hflags & MIPS_HFLAG_DM)) {
+ env->CP0_BadVAddr = arg;
+ }
+ do_raise_exception(env, EXCP_AdEL, ra);
+ }
+ env->CP0_LLAddr = cpu_mips_translate_address(env, arg, MMU_DATA_LOAD, ra);
+ env->llval = cpu_load_mmu(env, arg, oi, ra);
+ env->lladdr = arg;
+
+ return env->llval;
}
static target_ulong loads4(CPUMIPSState *env, target_ulong arg,
@@ -53,16 +56,24 @@ static target_ulong loads4(CPUMIPSState *env, target_ulong arg,
{
return (target_long)(int32_t)cpu_ldl_mmu(env, arg, oi, ra);
}
-HELPER_LD_ATOMIC(ll, loads4)
+
+target_ulong helper_ll(CPUMIPSState *env, target_ulong arg, int memop_idx)
+{
+ return do_ll(loads4, env, arg, memop_idx, GETPC());
+}
+
#ifdef TARGET_MIPS64
static target_ulong loadu8(CPUMIPSState *env, target_ulong arg,
MemOpIdx oi, uintptr_t ra)
{
return (target_ulong)cpu_ldq_mmu(env, arg, oi, ra);
}
-HELPER_LD_ATOMIC(lld, loadu8)
+
+target_ulong helper_lld(CPUMIPSState *env, target_ulong arg, int memop_idx)
+{
+ return do_ll(loadu8, env, arg, memop_idx, GETPC());
+}
#endif
-#undef HELPER_LD_ATOMIC
#endif /* !CONFIG_USER_ONLY */
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 17/22] target/mips: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 16/22] target/mips: Expand HELPER_LD_ATOMIC() Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-12 16:55 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 18/22] target/ppc: Inline cpu_ld/st_data_ra() calls in do_hash() Philippe Mathieu-Daudé
` (4 subsequent siblings)
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
In preparation of removing the cpu_ld*_mmuidx_ra() and
cpu_st*_mmuidx_ra() calls, inline them. Expand MO_TE to
mo_endian_env(env).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/ldst_helper.c | 49 +++++++++++++++++++----------------
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
index f3652034afa..716b60e3a39 100644
--- a/target/mips/tcg/ldst_helper.c
+++ b/target/mips/tcg/ldst_helper.c
@@ -237,8 +237,10 @@ void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
- uint32_t mem_idx)
+ uint32_t mmu_idx)
{
+ MemOp op = mo_endian_env(env) | MO_UL | MO_UNALN;
+ MemOpIdx oi = make_memop_idx(op, mmu_idx);
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
@@ -247,20 +249,22 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
for (i = 0; i < base_reglist; i++) {
env->active_tc.gpr[multiple_regs[i]] =
- (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
+ (target_long)cpu_ldl_mmu(env, addr, oi, GETPC());
addr += 4;
}
}
if (do_r31) {
env->active_tc.gpr[31] =
- (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
+ (target_long)cpu_ldl_mmu(env, addr, oi, GETPC());
}
}
void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
- uint32_t mem_idx)
+ uint32_t mmu_idx)
{
+ MemOp op = mo_endian_env(env) | MO_UL | MO_UNALN;
+ MemOpIdx oi = make_memop_idx(op, mmu_idx);
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
@@ -268,58 +272,59 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
target_ulong i;
for (i = 0; i < base_reglist; i++) {
- cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
- mem_idx, GETPC());
+ cpu_stl_mmu(env, addr, env->active_tc.gpr[multiple_regs[i]],
+ oi, GETPC());
addr += 4;
}
}
if (do_r31) {
- cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
+ cpu_stl_mmu(env, addr, env->active_tc.gpr[31], oi, GETPC());
}
}
#if defined(TARGET_MIPS64)
void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
- uint32_t mem_idx)
+ uint32_t mmu_idx)
{
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
+ uintptr_t retaddr = GETPC();
+ MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UQ | MO_UNALN,
+ mmu_idx);
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
- target_ulong i;
-
- for (i = 0; i < base_reglist; i++) {
- env->active_tc.gpr[multiple_regs[i]] =
- cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
+ for (unsigned i = 0; i < base_reglist; i++) {
+ env->active_tc.gpr[multiple_regs[i]] = cpu_ldq_mmu(env, addr,
+ oi, retaddr);
addr += 8;
}
}
if (do_r31) {
- env->active_tc.gpr[31] =
- cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
+ env->active_tc.gpr[31] = cpu_ldq_mmu(env, addr, oi, retaddr);
}
}
void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
- uint32_t mem_idx)
+ uint32_t mmu_idx)
{
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
+ uintptr_t retaddr = GETPC();
+ MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UQ | MO_UNALN,
+ mmu_idx);
if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
- target_ulong i;
-
- for (i = 0; i < base_reglist; i++) {
- cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
- mem_idx, GETPC());
+ for (unsigned i = 0; i < base_reglist; i++) {
+ cpu_stq_mmu(env, addr, env->active_tc.gpr[multiple_regs[i]],
+ oi, retaddr);
addr += 8;
}
}
if (do_r31) {
- cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
+ cpu_stq_mmu(env, addr, env->active_tc.gpr[31], oi, retaddr);
}
}
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 18/22] target/ppc: Inline cpu_ld/st_data_ra() calls in do_hash()
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 17/22] target/mips: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-12 16:57 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 19/22] target/ppc: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers Philippe Mathieu-Daudé
` (3 subsequent siblings)
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Nicholas Piggin, Chinmay Rath
In preparation of removing the cpu_ld*_data_ra()
and cpu_st*_data_ra() calls, inline them.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/ppc/tcg-excp_helper.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c
index edecfb85725..244aeb23c16 100644
--- a/target/ppc/tcg-excp_helper.c
+++ b/target/ppc/tcg-excp_helper.c
@@ -160,14 +160,17 @@ static void do_hash(CPUPPCState *env, target_ulong ea, target_ulong ra,
target_ulong rb, uint64_t key, bool store)
{
uint64_t calculated_hash = hash_digest(ra, rb, key), loaded_hash;
+ unsigned mmu_idx = cpu_mmu_index(env_cpu(env), false);
+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UQ | MO_UNALN, mmu_idx);
+ uintptr_t retaddr = GETPC();
if (store) {
- cpu_stq_data_ra(env, ea, calculated_hash, GETPC());
+ cpu_stq_mmu(env, ea, calculated_hash, oi, retaddr);
} else {
- loaded_hash = cpu_ldq_data_ra(env, ea, GETPC());
+ loaded_hash = cpu_ldq_mmu(env, ea, oi, retaddr);
if (loaded_hash != calculated_hash) {
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_TRAP, GETPC());
+ POWERPC_EXCP_TRAP, retaddr);
}
}
}
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 19/22] target/ppc: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 18/22] target/ppc: Inline cpu_ld/st_data_ra() calls in do_hash() Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-12 16:59 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 20/22] target/ppc: Inline cpu_ldl_data_ra() calls in ICBI helper Philippe Mathieu-Daudé
` (2 subsequent siblings)
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Nicholas Piggin, Chinmay Rath
In preparation of removing the cpu_ld*_mmuidx_ra() and
cpu_st*_mmuidx_ra() calls, inline them.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/ppc/mem_helper.c | 36 ++++++++++++++++++++++++++----------
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 6ab71a6fcb4..a43726d4223 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -97,8 +97,10 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
}
} else {
/* Slow path -- at least some of the operation requires i/o. */
+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_UNALN, mmu_idx);
+
for (; reg < 32; reg++) {
- env->gpr[reg] = cpu_ldl_mmuidx_ra(env, addr, mmu_idx, raddr);
+ env->gpr[reg] = cpu_ldl_mmu(env, addr, oi, raddr);
addr = addr_add(env, addr, 4);
}
}
@@ -120,7 +122,9 @@ void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
} else {
/* Slow path -- at least some of the operation requires i/o. */
for (; reg < 32; reg++) {
- cpu_stl_mmuidx_ra(env, addr, env->gpr[reg], mmu_idx, raddr);
+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_UNALN, mmu_idx);
+
+ cpu_stl_mmu(env, addr, env->gpr[reg], oi, raddr);
addr = addr_add(env, addr, 4);
}
}
@@ -161,9 +165,11 @@ static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
break;
}
} else {
+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_UNALN, mmu_idx);
+
/* Slow path -- at least some of the operation requires i/o. */
for (; nb > 3; nb -= 4) {
- env->gpr[reg] = cpu_ldl_mmuidx_ra(env, addr, mmu_idx, raddr);
+ env->gpr[reg] = cpu_ldl_mmu(env, addr, oi, raddr);
reg = (reg + 1) % 32;
addr = addr_add(env, addr, 4);
}
@@ -174,10 +180,12 @@ static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
val = cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 24;
break;
case 2:
- val = cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16;
+ oi = make_memop_idx(MO_TE | MO_UW | MO_UNALN, mmu_idx);
+ val = cpu_ldw_mmu(env, addr, oi, raddr) << 16;
break;
case 3:
- val = cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16;
+ oi = make_memop_idx(MO_TE | MO_UW | MO_UNALN, mmu_idx);
+ val = cpu_ldw_mmu(env, addr, oi, raddr) << 16;
addr = addr_add(env, addr, 2);
val |= cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 8;
break;
@@ -250,8 +258,11 @@ void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
break;
}
} else {
+ MemOpIdx oi;
+
+ oi = make_memop_idx(MO_TE | MO_UL | MO_UNALN, mmu_idx);
for (; nb > 3; nb -= 4) {
- cpu_stl_mmuidx_ra(env, addr, env->gpr[reg], mmu_idx, raddr);
+ cpu_stl_mmu(env, addr, env->gpr[reg], oi, raddr);
reg = (reg + 1) % 32;
addr = addr_add(env, addr, 4);
}
@@ -261,10 +272,12 @@ void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
cpu_stb_mmuidx_ra(env, addr, val >> 24, mmu_idx, raddr);
break;
case 2:
- cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr);
+ oi = make_memop_idx(MO_TE | MO_UW | MO_UNALN, mmu_idx);
+ cpu_stw_mmu(env, addr, val >> 16, oi, raddr);
break;
case 3:
- cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr);
+ oi = make_memop_idx(MO_TE | MO_UW | MO_UNALN, mmu_idx);
+ cpu_stw_mmu(env, addr, val >> 16, oi, raddr);
addr = addr_add(env, addr, 2);
cpu_stb_mmuidx_ra(env, addr, val >> 8, mmu_idx, raddr);
break;
@@ -293,8 +306,10 @@ static void dcbz_common(CPUPPCState *env, target_ulong addr,
haddr = probe_write(env, addr, dcbz_size, mmu_idx, retaddr);
if (unlikely(!haddr)) {
/* Slow path */
+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UQ | MO_UNALN, mmu_idx);
+
for (int i = 0; i < dcbz_size; i += 8) {
- cpu_stq_mmuidx_ra(env, addr + i, 0, mmu_idx, retaddr);
+ cpu_stq_mmu(env, addr + i, 0, oi, retaddr);
}
return;
}
@@ -342,9 +357,10 @@ void helper_icbi(CPUPPCState *env, target_ulong addr)
void helper_icbiep(CPUPPCState *env, target_ulong addr)
{
#if !defined(CONFIG_USER_ONLY)
+ MemOpIdx oi = make_memop_idx(MO_UL | MO_UNALN, PPC_TLB_EPID_LOAD);
/* See comments above */
addr &= ~(env->dcache_line_size - 1);
- cpu_ldl_mmuidx_ra(env, addr, PPC_TLB_EPID_LOAD, GETPC());
+ cpu_ldl_mmu(env, addr, oi, GETPC());
#endif
}
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 20/22] target/ppc: Inline cpu_ldl_data_ra() calls in ICBI helper
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 19/22] target/ppc: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-12 17:01 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 21/22] target/ppc: Simplify endianness handling in Altivec opcodes Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 22/22] accel/tcg: Remove non-explicit endian cpu_ld/st*_data*() helpers Philippe Mathieu-Daudé
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Nicholas Piggin, Chinmay Rath
Inline the cpu_ldl_data_ra() call in preparation of
removing it. Since the returned value is discarded,
don't bother to set the access endianness.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/ppc/mem_helper.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index a43726d4223..cff385b6020 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -344,14 +344,18 @@ void helper_dcbzl(CPUPPCState *env, target_ulong addr)
void helper_icbi(CPUPPCState *env, target_ulong addr)
{
+ unsigned mmu_idx = cpu_mmu_index(env_cpu(env), false);
+ MemOpIdx oi = make_memop_idx(MO_UL | MO_UNALN, mmu_idx);
+
addr &= ~(env->dcache_line_size - 1);
/*
* Invalidate one cache line :
* PowerPC specification says this is to be treated like a load
* (not a fetch) by the MMU. To be sure it will be so,
- * do the load "by hand".
+ * do the load "by hand". As the returned data is not consumed,
+ * endianness is irrelevant.
*/
- cpu_ldl_data_ra(env, addr, GETPC());
+ cpu_ldl_mmu(env, addr, oi, GETPC());
}
void helper_icbiep(CPUPPCState *env, target_ulong addr)
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 21/22] target/ppc: Simplify endianness handling in Altivec opcodes
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (19 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 20/22] target/ppc: Inline cpu_ldl_data_ra() calls in ICBI helper Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-12-12 17:02 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 22/22] accel/tcg: Remove non-explicit endian cpu_ld/st*_data*() helpers Philippe Mathieu-Daudé
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Nicholas Piggin, Chinmay Rath
Access the memory in big-endian order, swap bytes
when MSR.LE is set.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/ppc/mem_helper.c | 31 ++++++++++---------------------
1 file changed, 10 insertions(+), 21 deletions(-)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index cff385b6020..cfc67a527c1 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -31,15 +31,6 @@
/* #define DEBUG_OP */
-static inline bool needs_byteswap(const CPUPPCState *env)
-{
-#if TARGET_BIG_ENDIAN
- return FIELD_EX64(env->msr, MSR, LE);
-#else
- return !FIELD_EX64(env->msr, MSR, LE);
-#endif
-}
-
/*****************************************************************************/
/* Memory load and stores */
@@ -421,11 +412,10 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
int adjust = HI_IDX * (n_elems - 1); \
int sh = sizeof(r->element[0]) >> 1; \
int index = (addr & 0xf) >> sh; \
- if (FIELD_EX64(env->msr, MSR, LE)) { \
- index = n_elems - index - 1; \
- } \
+ bool byteswap = FIELD_EX64(env->msr, MSR, LE); \
\
- if (needs_byteswap(env)) { \
+ if (byteswap) { \
+ index = n_elems - index - 1; \
r->element[LO_IDX ? index : (adjust - index)] = \
swap(access(env, addr, GETPC())); \
} else { \
@@ -435,8 +425,8 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg,
}
#define I(x) (x)
LVE(LVEBX, cpu_ldub_data_ra, I, u8)
-LVE(LVEHX, cpu_lduw_data_ra, bswap16, u16)
-LVE(LVEWX, cpu_ldl_data_ra, bswap32, u32)
+LVE(LVEHX, cpu_lduw_be_data_ra, bswap16, u16)
+LVE(LVEWX, cpu_ldl_be_data_ra, bswap32, u32)
#undef I
#undef LVE
@@ -448,11 +438,10 @@ LVE(LVEWX, cpu_ldl_data_ra, bswap32, u32)
int adjust = HI_IDX * (n_elems - 1); \
int sh = sizeof(r->element[0]) >> 1; \
int index = (addr & 0xf) >> sh; \
- if (FIELD_EX64(env->msr, MSR, LE)) { \
- index = n_elems - index - 1; \
- } \
+ bool byteswap = FIELD_EX64(env->msr, MSR, LE); \
\
- if (needs_byteswap(env)) { \
+ if (byteswap) { \
+ index = n_elems - index - 1; \
access(env, addr, swap(r->element[LO_IDX ? index : \
(adjust - index)]), \
GETPC()); \
@@ -463,8 +452,8 @@ LVE(LVEWX, cpu_ldl_data_ra, bswap32, u32)
}
#define I(x) (x)
STVE(STVEBX, cpu_stb_data_ra, I, u8)
-STVE(STVEHX, cpu_stw_data_ra, bswap16, u16)
-STVE(STVEWX, cpu_stl_data_ra, bswap32, u32)
+STVE(STVEHX, cpu_stw_be_data_ra, bswap16, u16)
+STVE(STVEWX, cpu_stl_be_data_ra, bswap32, u32)
#undef I
#undef LVE
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH-for-11.0 v3 22/22] accel/tcg: Remove non-explicit endian cpu_ld/st*_data*() helpers
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
` (20 preceding siblings ...)
2025-11-26 20:21 ` [PATCH-for-11.0 v3 21/22] target/ppc: Simplify endianness handling in Altivec opcodes Philippe Mathieu-Daudé
@ 2025-11-26 20:21 ` Philippe Mathieu-Daudé
2025-11-26 20:32 ` Philippe Mathieu-Daudé
21 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:21 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Philippe Mathieu-Daudé, Paolo Bonzini
All uses were converted to the explicit cpu_ld/st*_{be,le}_data*()
helpers, no need for the non-explicit versions anymore.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/accel/tcg/cpu-ldst.h | 46 ------------------------------------
1 file changed, 46 deletions(-)
diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h
index 0de7f5eaa6b..12dd38599a6 100644
--- a/include/accel/tcg/cpu-ldst.h
+++ b/include/accel/tcg/cpu-ldst.h
@@ -428,52 +428,6 @@ cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64_t val)
cpu_stq_le_data_ra(env, addr, val, 0);
}
-#if TARGET_BIG_ENDIAN
-# define cpu_lduw_data cpu_lduw_be_data
-# define cpu_ldsw_data cpu_ldsw_be_data
-# define cpu_ldl_data cpu_ldl_be_data
-# define cpu_ldq_data cpu_ldq_be_data
-# define cpu_lduw_data_ra cpu_lduw_be_data_ra
-# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
-# define cpu_ldl_data_ra cpu_ldl_be_data_ra
-# define cpu_ldq_data_ra cpu_ldq_be_data_ra
-# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
-# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
-# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
-# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
-# define cpu_stw_data cpu_stw_be_data
-# define cpu_stl_data cpu_stl_be_data
-# define cpu_stq_data cpu_stq_be_data
-# define cpu_stw_data_ra cpu_stw_be_data_ra
-# define cpu_stl_data_ra cpu_stl_be_data_ra
-# define cpu_stq_data_ra cpu_stq_be_data_ra
-# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
-# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
-# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
-#else
-# define cpu_lduw_data cpu_lduw_le_data
-# define cpu_ldsw_data cpu_ldsw_le_data
-# define cpu_ldl_data cpu_ldl_le_data
-# define cpu_ldq_data cpu_ldq_le_data
-# define cpu_lduw_data_ra cpu_lduw_le_data_ra
-# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
-# define cpu_ldl_data_ra cpu_ldl_le_data_ra
-# define cpu_ldq_data_ra cpu_ldq_le_data_ra
-# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
-# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
-# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
-# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
-# define cpu_stw_data cpu_stw_le_data
-# define cpu_stl_data cpu_stl_le_data
-# define cpu_stq_data cpu_stq_le_data
-# define cpu_stw_data_ra cpu_stw_le_data_ra
-# define cpu_stl_data_ra cpu_stl_le_data_ra
-# define cpu_stq_data_ra cpu_stq_le_data_ra
-# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
-# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
-# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
-#endif
-
static inline uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
{
CPUState *cs = env_cpu(env);
--
2.51.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 22/22] accel/tcg: Remove non-explicit endian cpu_ld/st*_data*() helpers
2025-11-26 20:21 ` [PATCH-for-11.0 v3 22/22] accel/tcg: Remove non-explicit endian cpu_ld/st*_data*() helpers Philippe Mathieu-Daudé
@ 2025-11-26 20:32 ` Philippe Mathieu-Daudé
2025-12-12 17:02 ` Richard Henderson
0 siblings, 1 reply; 39+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-26 20:32 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-s390x, Richard Henderson, qemu-riscv, qemu-ppc,
Paolo Bonzini, Peter Maydell
On 26/11/25 21:21, Philippe Mathieu-Daudé wrote:
> All uses were converted to the explicit cpu_ld/st*_{be,le}_data*()
> helpers, no need for the non-explicit versions anymore.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> include/accel/tcg/cpu-ldst.h | 46 ------------------------------------
> 1 file changed, 46 deletions(-)
>
> diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h
> index 0de7f5eaa6b..12dd38599a6 100644
> --- a/include/accel/tcg/cpu-ldst.h
> +++ b/include/accel/tcg/cpu-ldst.h
> @@ -428,52 +428,6 @@ cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64_t val)
> cpu_stq_le_data_ra(env, addr, val, 0);
> }
>
> -#if TARGET_BIG_ENDIAN
> -# define cpu_lduw_data cpu_lduw_be_data
> -# define cpu_ldsw_data cpu_ldsw_be_data
> -# define cpu_ldl_data cpu_ldl_be_data
> -# define cpu_ldq_data cpu_ldq_be_data
> -# define cpu_lduw_data_ra cpu_lduw_be_data_ra
> -# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
> -# define cpu_ldl_data_ra cpu_ldl_be_data_ra
> -# define cpu_ldq_data_ra cpu_ldq_be_data_ra
> -# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
> -# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
> -# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
> -# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
> -# define cpu_stw_data cpu_stw_be_data
> -# define cpu_stl_data cpu_stl_be_data
> -# define cpu_stq_data cpu_stq_be_data
> -# define cpu_stw_data_ra cpu_stw_be_data_ra
> -# define cpu_stl_data_ra cpu_stl_be_data_ra
> -# define cpu_stq_data_ra cpu_stq_be_data_ra
> -# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
> -# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
> -# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
> -#else
> -# define cpu_lduw_data cpu_lduw_le_data
> -# define cpu_ldsw_data cpu_ldsw_le_data
> -# define cpu_ldl_data cpu_ldl_le_data
> -# define cpu_ldq_data cpu_ldq_le_data
> -# define cpu_lduw_data_ra cpu_lduw_le_data_ra
> -# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
> -# define cpu_ldl_data_ra cpu_ldl_le_data_ra
> -# define cpu_ldq_data_ra cpu_ldq_le_data_ra
> -# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
> -# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
> -# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
> -# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
> -# define cpu_stw_data cpu_stw_le_data
> -# define cpu_stl_data cpu_stl_le_data
> -# define cpu_stq_data cpu_stq_le_data
> -# define cpu_stw_data_ra cpu_stw_le_data_ra
> -# define cpu_stl_data_ra cpu_stl_le_data_ra
> -# define cpu_stq_data_ra cpu_stq_le_data_ra
> -# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
> -# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
> -# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
> -#endif
> -
Missing to squash:
-- >8 --
diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst
index c906c6509ee..e956aece673 100644
--- a/docs/devel/loads-stores.rst
+++ b/docs/devel/loads-stores.rst
@@ -152,3 +152,3 @@ store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val,
mmuidx, retaddr)``
``end``
- - (empty) : for target endian, or 8 bit sizes
+ - (empty) : for 8 bit sizes
- ``_be`` : big endian
@@ -157,4 +157,4 @@ store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val,
mmuidx, retaddr)``
Regexes for git grep:
- - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_mmuidx_ra\>``
- - ``\<cpu_st[bwlq]\(_[bl]e\)\?_mmuidx_ra\>``
+ - ``\<cpu_ld[us]\?\(b\|[wlq]\(_[bl]e\)\)_mmuidx_ra\>``
+ - ``\<cpu_st\(b\|[wlq]\(_[bl]e\)\)_mmuidx_ra\>``
@@ -190,3 +190,3 @@ store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``
``end``
- - (empty) : for target endian, or 8 bit sizes
+ - (empty) : for 8 bit sizes
- ``_be`` : big endian
@@ -195,4 +195,4 @@ store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``
Regexes for git grep:
- - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_data_ra\>``
- - ``\<cpu_st[bwlq]\(_[bl]e\)\?_data_ra\>``
+ - ``\<cpu_ld[us]\?\(b\|[wlq]\(_[bl]e\)\)_data_ra\>``
+ - ``\<cpu_st\(b\|[wlq]\(_[bl]e\)\)_data_ra\>``
@@ -229,3 +229,3 @@ store: ``cpu_st{size}{end}_data(env, ptr, val)``
``end``
- - (empty) : for target endian, or 8 bit sizes
+ - (empty) : for 8 bit sizes
- ``_be`` : big endian
@@ -234,4 +234,4 @@ store: ``cpu_st{size}{end}_data(env, ptr, val)``
Regexes for git grep:
- - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_data\>``
- - ``\<cpu_st[bwlq]\(_[bl]e\)\?_data\+\>``
+ - ``\<cpu_ld[us]\?\(b\|[wlq]\(_[bl]e\)\)_data\>``
+ - ``\<cpu_st\(b\|[wlq]\(_[bl]e\)\)_data\+\>``
---
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 07/22] target/m68k: Use big-endian variant of cpu_ld/st_data*()
2025-11-26 20:21 ` [PATCH-for-11.0 v3 07/22] target/m68k: " Philippe Mathieu-Daudé
@ 2025-12-05 20:02 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-05 20:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Laurent Vivier
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> We only build the M68k target using big endianness order,
> therefore the cpu_ld/st_data*() definitions expand to the
> big endian declarations. Use the explicit big-endian variants.
>
> Mechanical change running:
>
> $ tgt=m68k; \
> end=be; \
> for op in data mmuidx_ra; do \
> for ac in uw sw l q; do \
> sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
> $(git grep -l cpu_ target/${tgt}/); \
> done;
> for ac in w l q; do \
> sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
> $(git grep -l cpu_ target/${tgt}/); \
> done;
> done
>
> Then adapting indentation in do_stack_frame() to pass checkpatch.pl.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/m68k/fpu_helper.c | 12 +++---
> target/m68k/op_helper.c | 91 ++++++++++++++++++++--------------------
> 2 files changed, 52 insertions(+), 51 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 10/22] target/sh4: Replace cpu_stl_data() call in OCBI helper
2025-11-26 20:21 ` [PATCH-for-11.0 v3 10/22] target/sh4: Replace cpu_stl_data() call in OCBI helper Philippe Mathieu-Daudé
@ 2025-12-05 20:03 ` Richard Henderson
2025-12-05 20:06 ` Richard Henderson
1 sibling, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-05 20:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Yoshinori Sato
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> In preparation of removing the cpu_stl_data() call,
> inline it. Set the return address argument.
>
> See commit 852d481faf7 ("SH: Improve movca.l/ocbi
> emulation") for more context on this code.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/sh4/op_helper.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 10/22] target/sh4: Replace cpu_stl_data() call in OCBI helper
2025-11-26 20:21 ` [PATCH-for-11.0 v3 10/22] target/sh4: Replace cpu_stl_data() call in OCBI helper Philippe Mathieu-Daudé
2025-12-05 20:03 ` Richard Henderson
@ 2025-12-05 20:06 ` Richard Henderson
1 sibling, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-05 20:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Yoshinori Sato
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> In preparation of removing the cpu_stl_data() call,
> inline it. Set the return address argument.
>
> See commit 852d481faf7 ("SH: Improve movca.l/ocbi
> emulation") for more context on this code.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/sh4/op_helper.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 11/22] target/mips: Use big-endian variant of cpu_ld/st_data*() for MSA opcode
2025-11-26 20:21 ` [PATCH-for-11.0 v3 11/22] target/mips: Use big-endian variant of cpu_ld/st_data*() for MSA opcode Philippe Mathieu-Daudé
@ 2025-12-12 16:28 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 16:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> MSA vectors are accessed in big endianness.
>
> Per the "MIPS® SIMD Architecture" (MD00926 rev 1.03):
>
> 3.1 Registers Layout
>
> MSA vectors are stored in memory starting from the 0th element at
> the lowest byte address. The byte order of each element follows the
> big- or little-endian convention of the system configuration.
This says "follow the system configuration" ...
>
> Use the explicit big-endian variants of cpu_ld/st_data*().
... so how do you get "big-endian" from that?
> diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
> index f554b3d10ee..d6ce17abf9a 100644
> --- a/target/mips/tcg/msa_helper.c
> +++ b/target/mips/tcg/msa_helper.c
> @@ -8231,8 +8231,8 @@ void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
> uint64_t d0, d1;
>
> /* Load 8 bytes at a time. Vector element ordering makes this LE. */
> - d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);
> - d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);
> + d0 = cpu_ldq_be_data_ra(env, addr + 0, ra);
> + d1 = cpu_ldq_be_data_ra(env, addr + 8, ra);
> pwd->d[0] = d0;
> pwd->d[1] = d1;
This really seems to be exchanging one bug for another.
And the comment no longer matches.
Also, this would be much better accomplished inline as
tcg_gen_ld_i128(..., mo_endian(s) | MO_128 | MO_ATOM_<something>);
where <something> will be MO_ATOM_NONE for vector of 1-byte elements, MO_ATOM_IFALIGN_PAIR
for 8-byte elements, and MO_ATOM_SUBALIGN for the others (which is slightly stronger than
required, but we don't have MO_ATOM_IFALIGN_<N> for all N).
Doing that for the stores as well will allow removal of ...
> ensure_writable_pages(env, addr, mmu_idx, GETPC());
... this hack.
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 12/22] target/mips: Introduce loadu8() & loads4() helpers
2025-11-26 20:21 ` [PATCH-for-11.0 v3 12/22] target/mips: Introduce loadu8() & loads4() helpers Philippe Mathieu-Daudé
@ 2025-12-12 16:32 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 16:32 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> +static target_ulong loads4(CPUMIPSState *env, target_ulong arg,
> + unsigned mem_idx, uintptr_t ra)
> +{
> + return (target_long)(int32_t)cpu_ldl_mmuidx_ra(env, arg, mem_idx, ra);
> +}
> +HELPER_LD_ATOMIC(ll, 0x3, loads4)
> #ifdef TARGET_MIPS64
> -HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
> +static target_ulong loadu8(CPUMIPSState *env, target_ulong arg,
> + unsigned mem_idx, uintptr_t ra)
> +{
> + return (target_ulong)cpu_ldq_mmuidx_ra(env, arg, mem_idx, ra);
> +}
You don't need the casts to target_ulong -- those are implied by the return type.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 13/22] target/mips: Pass MemOpIdx to atomic load helpers
2025-11-26 20:21 ` [PATCH-for-11.0 v3 13/22] target/mips: Pass MemOpIdx to atomic load helpers Philippe Mathieu-Daudé
@ 2025-12-12 16:33 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 16:33 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> Pass a full MemOpIdx at translation, then recover the
> MMU index calling get_mmuidx() in the helper.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/tcg/ldst_helper.c | 4 +++-
> target/mips/tcg/translate.c | 9 +++++----
> 2 files changed, 8 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
>
> diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
> index c1c4a60cf3f..013cd825dac 100644
> --- a/target/mips/tcg/ldst_helper.c
> +++ b/target/mips/tcg/ldst_helper.c
> @@ -30,8 +30,10 @@
> #ifndef CONFIG_USER_ONLY
>
> #define HELPER_LD_ATOMIC(name, almask, cpu_load) \
> -target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
> +target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int memop_idx)\
> { \
> + MemOpIdx oi = memop_idx; \
> + unsigned mem_idx = get_mmuidx(oi); \
> if (arg & almask) { \
> if (!(env->hflags & MIPS_HFLAG_DM)) { \
> env->CP0_BadVAddr = arg; \
> diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
> index 54849e9ff1a..c476271d6d5 100644
> --- a/target/mips/tcg/translate.c
> +++ b/target/mips/tcg/translate.c
> @@ -1932,16 +1932,17 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
> tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); \
> }
> #else
> -#define OP_LD_ATOMIC(insn, ignored_memop) \
> +#define OP_LD_ATOMIC(insn, mop) \
> static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
> DisasContext *ctx) \
> { \
> - gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \
> + MemOpIdx oi = make_memop_idx(mop | mo_endian(ctx), mem_idx); \
> + gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(oi)); \
> }
> #endif
> -OP_LD_ATOMIC(ll, mo_endian(ctx) | MO_SL);
> +OP_LD_ATOMIC(ll, MO_SL);
> #if defined(TARGET_MIPS64)
> -OP_LD_ATOMIC(lld, mo_endian(ctx) | MO_UQ);
> +OP_LD_ATOMIC(lld, MO_UQ);
> #endif
> #undef OP_LD_ATOMIC
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 14/22] target/mips: Drop almask argument of HELPER_LD_ATOMIC() macro
2025-11-26 20:21 ` [PATCH-for-11.0 v3 14/22] target/mips: Drop almask argument of HELPER_LD_ATOMIC() macro Philippe Mathieu-Daudé
@ 2025-12-12 16:35 ` Richard Henderson
2025-12-12 16:43 ` Richard Henderson
0 siblings, 1 reply; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 16:35 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> HELPER_LD_ATOMIC() now has a MemOpIdx, from which we
> can extract the MemOp size. Use it to check the address
> alignment.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/tcg/ldst_helper.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
True, but adding MO_ALIGN to the MemOpIdx (and thus to the MemOp) might be more useful,
allowing you to remove this explicit check.
r~
>
> diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
> index 013cd825dac..bef384575c2 100644
> --- a/target/mips/tcg/ldst_helper.c
> +++ b/target/mips/tcg/ldst_helper.c
> @@ -29,12 +29,14 @@
>
> #ifndef CONFIG_USER_ONLY
>
> -#define HELPER_LD_ATOMIC(name, almask, cpu_load) \
> +#define HELPER_LD_ATOMIC(name, cpu_load) \
> target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int memop_idx)\
> { \
> MemOpIdx oi = memop_idx; \
> unsigned mem_idx = get_mmuidx(oi); \
> - if (arg & almask) { \
> + MemOp op = get_memop(oi); \
> + unsigned size = memop_size(op); \
> + if (arg & (size - 1)) { \
> if (!(env->hflags & MIPS_HFLAG_DM)) { \
> env->CP0_BadVAddr = arg; \
> } \
> @@ -52,14 +54,14 @@ static target_ulong loads4(CPUMIPSState *env, target_ulong arg,
> {
> return (target_long)(int32_t)cpu_ldl_mmuidx_ra(env, arg, mem_idx, ra);
> }
> -HELPER_LD_ATOMIC(ll, 0x3, loads4)
> +HELPER_LD_ATOMIC(ll, loads4)
> #ifdef TARGET_MIPS64
> static target_ulong loadu8(CPUMIPSState *env, target_ulong arg,
> unsigned mem_idx, uintptr_t ra)
> {
> return (target_ulong)cpu_ldq_mmuidx_ra(env, arg, mem_idx, ra);
> }
> -HELPER_LD_ATOMIC(lld, 0x7, loadu8)
> +HELPER_LD_ATOMIC(lld, loadu8)
> #endif
> #undef HELPER_LD_ATOMIC
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 14/22] target/mips: Drop almask argument of HELPER_LD_ATOMIC() macro
2025-12-12 16:35 ` Richard Henderson
@ 2025-12-12 16:43 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 16:43 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
On 12/12/25 10:35, Richard Henderson wrote:
> On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
>> HELPER_LD_ATOMIC() now has a MemOpIdx, from which we
>> can extract the MemOp size. Use it to check the address
>> alignment.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> target/mips/tcg/ldst_helper.c | 10 ++++++----
>> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> True, but adding MO_ALIGN to the MemOpIdx (and thus to the MemOp) might be more useful,
> allowing you to remove this explicit check.
Follow-up: You'd also reorg the function such that
env->llval = cpu_load(env, arg, oi, GETPC()); \
env->CP0_LLAddr = cpu_mips_translate_address(env, arg, MMU_DATA_LOAD, \
GETPC()); \
env->lladdr = arg; \
return env->llval; \
so that lladdr and CP0_LLAddr do not get assigned when there is an alignment fault.
Also, the cpu_load will have either faulted, or pulled in the translation to CPUTLB. You
don't need the full PTW of cpu_mips_translate_address. Using probe_access_full will
quickly grab the CPUTLBEntryFull, from which phys_addr is your required value.
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 16/22] target/mips: Expand HELPER_LD_ATOMIC()
2025-11-26 20:21 ` [PATCH-for-11.0 v3 16/22] target/mips: Expand HELPER_LD_ATOMIC() Philippe Mathieu-Daudé
@ 2025-12-12 16:46 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 16:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> Since it is easier to maintain a plain C function,
> expand the HELPER_LD_ATOMIC() macro as do_ll().
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/mips/tcg/ldst_helper.c | 51 +++++++++++++++++++++--------------
> 1 file changed, 31 insertions(+), 20 deletions(-)
It's worth looking to make sure these functions are inlined in the -O2 build.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 17/22] target/mips: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers
2025-11-26 20:21 ` [PATCH-for-11.0 v3 17/22] target/mips: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers Philippe Mathieu-Daudé
@ 2025-12-12 16:55 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 16:55 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> In preparation of removing the cpu_ld*_mmuidx_ra() and
> cpu_st*_mmuidx_ra() calls, inline them. Expand MO_TE to
> mo_endian_env(env).
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/tcg/ldst_helper.c | 49 +++++++++++++++++++----------------
> 1 file changed, 27 insertions(+), 22 deletions(-)
>
> diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
> index f3652034afa..716b60e3a39 100644
> --- a/target/mips/tcg/ldst_helper.c
> +++ b/target/mips/tcg/ldst_helper.c
> @@ -237,8 +237,10 @@ void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
> static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
>
> void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
> - uint32_t mem_idx)
> + uint32_t mmu_idx)
> {
> + MemOp op = mo_endian_env(env) | MO_UL | MO_UNALN;
> + MemOpIdx oi = make_memop_idx(op, mmu_idx);
> target_ulong base_reglist = reglist & 0xf;
> target_ulong do_r31 = reglist & 0x10;
>
> @@ -247,20 +249,22 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
>
> for (i = 0; i < base_reglist; i++) {
> env->active_tc.gpr[multiple_regs[i]] =
> - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
> + (target_long)cpu_ldl_mmu(env, addr, oi, GETPC());
While this is a faithful expansion of cpu_ldl_mmuidx_ra, v5 micromips requires alignment
and v6 micromips does not. You may be better served passing the whole MemOpIdx down with
MO_ALIGN vs MO_UNALN.
Or, indeed, dropping the helper entirely and implementing the function inline -- this
maxes out at 10 load/stores after all.
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 18/22] target/ppc: Inline cpu_ld/st_data_ra() calls in do_hash()
2025-11-26 20:21 ` [PATCH-for-11.0 v3 18/22] target/ppc: Inline cpu_ld/st_data_ra() calls in do_hash() Philippe Mathieu-Daudé
@ 2025-12-12 16:57 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 16:57 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Nicholas Piggin, Chinmay Rath
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> In preparation of removing the cpu_ld*_data_ra()
> and cpu_st*_data_ra() calls, inline them.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/ppc/tcg-excp_helper.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c
> index edecfb85725..244aeb23c16 100644
> --- a/target/ppc/tcg-excp_helper.c
> +++ b/target/ppc/tcg-excp_helper.c
> @@ -160,14 +160,17 @@ static void do_hash(CPUPPCState *env, target_ulong ea, target_ulong ra,
> target_ulong rb, uint64_t key, bool store)
> {
> uint64_t calculated_hash = hash_digest(ra, rb, key), loaded_hash;
> + unsigned mmu_idx = cpu_mmu_index(env_cpu(env), false);
> + MemOpIdx oi = make_memop_idx(MO_TE | MO_UQ | MO_UNALN, mmu_idx);
> + uintptr_t retaddr = GETPC();
>
> if (store) {
> - cpu_stq_data_ra(env, ea, calculated_hash, GETPC());
> + cpu_stq_mmu(env, ea, calculated_hash, oi, retaddr);
> } else {
> - loaded_hash = cpu_ldq_data_ra(env, ea, GETPC());
> + loaded_hash = cpu_ldq_mmu(env, ea, oi, retaddr);
> if (loaded_hash != calculated_hash) {
> raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
> - POWERPC_EXCP_TRAP, GETPC());
> + POWERPC_EXCP_TRAP, retaddr);
> }
> }
> }
This is the page translation hash. I suspect the actual address must be aligned, and
probably forcibly so via computation. The MO_UNALN is either wrong or misleading.
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 19/22] target/ppc: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers
2025-11-26 20:21 ` [PATCH-for-11.0 v3 19/22] target/ppc: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers Philippe Mathieu-Daudé
@ 2025-12-12 16:59 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 16:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Nicholas Piggin, Chinmay Rath
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> @@ -342,9 +357,10 @@ void helper_icbi(CPUPPCState *env, target_ulong addr)
> void helper_icbiep(CPUPPCState *env, target_ulong addr)
> {
> #if !defined(CONFIG_USER_ONLY)
> + MemOpIdx oi = make_memop_idx(MO_UL | MO_UNALN, PPC_TLB_EPID_LOAD);
> /* See comments above */
> addr &= ~(env->dcache_line_size - 1);
> - cpu_ldl_mmuidx_ra(env, addr, PPC_TLB_EPID_LOAD, GETPC());
> + cpu_ldl_mmu(env, addr, oi, GETPC());
> #endif
> }
Missing MO_[TBL]E.
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 20/22] target/ppc: Inline cpu_ldl_data_ra() calls in ICBI helper
2025-11-26 20:21 ` [PATCH-for-11.0 v3 20/22] target/ppc: Inline cpu_ldl_data_ra() calls in ICBI helper Philippe Mathieu-Daudé
@ 2025-12-12 17:01 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 17:01 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Nicholas Piggin, Chinmay Rath
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> Inline the cpu_ldl_data_ra() call in preparation of
> removing it. Since the returned value is discarded,
> don't bother to set the access endianness.
>
Hah! The previous patch could have used the same comment.
Or maybe moving that hunk here.
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/ppc/mem_helper.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
> index a43726d4223..cff385b6020 100644
> --- a/target/ppc/mem_helper.c
> +++ b/target/ppc/mem_helper.c
> @@ -344,14 +344,18 @@ void helper_dcbzl(CPUPPCState *env, target_ulong addr)
>
> void helper_icbi(CPUPPCState *env, target_ulong addr)
> {
> + unsigned mmu_idx = cpu_mmu_index(env_cpu(env), false);
> + MemOpIdx oi = make_memop_idx(MO_UL | MO_UNALN, mmu_idx);
> +
> addr &= ~(env->dcache_line_size - 1);
> /*
> * Invalidate one cache line :
> * PowerPC specification says this is to be treated like a load
> * (not a fetch) by the MMU. To be sure it will be so,
> - * do the load "by hand".
> + * do the load "by hand". As the returned data is not consumed,
> + * endianness is irrelevant.
> */
> - cpu_ldl_data_ra(env, addr, GETPC());
> + cpu_ldl_mmu(env, addr, oi, GETPC());
> }
>
> void helper_icbiep(CPUPPCState *env, target_ulong addr)
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 21/22] target/ppc: Simplify endianness handling in Altivec opcodes
2025-11-26 20:21 ` [PATCH-for-11.0 v3 21/22] target/ppc: Simplify endianness handling in Altivec opcodes Philippe Mathieu-Daudé
@ 2025-12-12 17:02 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 17:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Nicholas Piggin, Chinmay Rath
On 11/26/25 14:21, Philippe Mathieu-Daudé wrote:
> Access the memory in big-endian order, swap bytes
> when MSR.LE is set.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/ppc/mem_helper.c | 31 ++++++++++---------------------
> 1 file changed, 10 insertions(+), 21 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH-for-11.0 v3 22/22] accel/tcg: Remove non-explicit endian cpu_ld/st*_data*() helpers
2025-11-26 20:32 ` Philippe Mathieu-Daudé
@ 2025-12-12 17:02 ` Richard Henderson
0 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2025-12-12 17:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-s390x, qemu-riscv, qemu-ppc, Paolo Bonzini, Peter Maydell
On 11/26/25 14:32, Philippe Mathieu-Daudé wrote:
> On 26/11/25 21:21, Philippe Mathieu-Daudé wrote:
>> All uses were converted to the explicit cpu_ld/st*_{be,le}_data*()
>> helpers, no need for the non-explicit versions anymore.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> include/accel/tcg/cpu-ldst.h | 46 ------------------------------------
>> 1 file changed, 46 deletions(-)
>>
>> diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h
>> index 0de7f5eaa6b..12dd38599a6 100644
>> --- a/include/accel/tcg/cpu-ldst.h
>> +++ b/include/accel/tcg/cpu-ldst.h
>> @@ -428,52 +428,6 @@ cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64_t val)
>> cpu_stq_le_data_ra(env, addr, val, 0);
>> }
>> -#if TARGET_BIG_ENDIAN
>> -# define cpu_lduw_data cpu_lduw_be_data
>> -# define cpu_ldsw_data cpu_ldsw_be_data
>> -# define cpu_ldl_data cpu_ldl_be_data
>> -# define cpu_ldq_data cpu_ldq_be_data
>> -# define cpu_lduw_data_ra cpu_lduw_be_data_ra
>> -# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
>> -# define cpu_ldl_data_ra cpu_ldl_be_data_ra
>> -# define cpu_ldq_data_ra cpu_ldq_be_data_ra
>> -# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
>> -# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
>> -# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
>> -# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
>> -# define cpu_stw_data cpu_stw_be_data
>> -# define cpu_stl_data cpu_stl_be_data
>> -# define cpu_stq_data cpu_stq_be_data
>> -# define cpu_stw_data_ra cpu_stw_be_data_ra
>> -# define cpu_stl_data_ra cpu_stl_be_data_ra
>> -# define cpu_stq_data_ra cpu_stq_be_data_ra
>> -# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
>> -# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
>> -# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
>> -#else
>> -# define cpu_lduw_data cpu_lduw_le_data
>> -# define cpu_ldsw_data cpu_ldsw_le_data
>> -# define cpu_ldl_data cpu_ldl_le_data
>> -# define cpu_ldq_data cpu_ldq_le_data
>> -# define cpu_lduw_data_ra cpu_lduw_le_data_ra
>> -# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
>> -# define cpu_ldl_data_ra cpu_ldl_le_data_ra
>> -# define cpu_ldq_data_ra cpu_ldq_le_data_ra
>> -# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
>> -# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
>> -# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
>> -# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
>> -# define cpu_stw_data cpu_stw_le_data
>> -# define cpu_stl_data cpu_stl_le_data
>> -# define cpu_stq_data cpu_stq_le_data
>> -# define cpu_stw_data_ra cpu_stw_le_data_ra
>> -# define cpu_stl_data_ra cpu_stl_le_data_ra
>> -# define cpu_stq_data_ra cpu_stq_le_data_ra
>> -# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
>> -# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
>> -# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
>> -#endif
>> -
>
> Missing to squash:
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
>
> -- >8 --
> diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst
> index c906c6509ee..e956aece673 100644
> --- a/docs/devel/loads-stores.rst
> +++ b/docs/devel/loads-stores.rst
> @@ -152,3 +152,3 @@ store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
> ``end``
> - - (empty) : for target endian, or 8 bit sizes
> + - (empty) : for 8 bit sizes
> - ``_be`` : big endian
> @@ -157,4 +157,4 @@ store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
> Regexes for git grep:
> - - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_mmuidx_ra\>``
> - - ``\<cpu_st[bwlq]\(_[bl]e\)\?_mmuidx_ra\>``
> + - ``\<cpu_ld[us]\?\(b\|[wlq]\(_[bl]e\)\)_mmuidx_ra\>``
> + - ``\<cpu_st\(b\|[wlq]\(_[bl]e\)\)_mmuidx_ra\>``
>
> @@ -190,3 +190,3 @@ store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``
> ``end``
> - - (empty) : for target endian, or 8 bit sizes
> + - (empty) : for 8 bit sizes
> - ``_be`` : big endian
> @@ -195,4 +195,4 @@ store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``
> Regexes for git grep:
> - - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_data_ra\>``
> - - ``\<cpu_st[bwlq]\(_[bl]e\)\?_data_ra\>``
> + - ``\<cpu_ld[us]\?\(b\|[wlq]\(_[bl]e\)\)_data_ra\>``
> + - ``\<cpu_st\(b\|[wlq]\(_[bl]e\)\)_data_ra\>``
>
> @@ -229,3 +229,3 @@ store: ``cpu_st{size}{end}_data(env, ptr, val)``
> ``end``
> - - (empty) : for target endian, or 8 bit sizes
> + - (empty) : for 8 bit sizes
> - ``_be`` : big endian
> @@ -234,4 +234,4 @@ store: ``cpu_st{size}{end}_data(env, ptr, val)``
> Regexes for git grep:
> - - ``\<cpu_ld[us]\?[bwlq]\(_[bl]e\)\?_data\>``
> - - ``\<cpu_st[bwlq]\(_[bl]e\)\?_data\+\>``
> + - ``\<cpu_ld[us]\?\(b\|[wlq]\(_[bl]e\)\)_data\>``
> + - ``\<cpu_st\(b\|[wlq]\(_[bl]e\)\)_data\+\>``
> ---
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2025-12-12 17:03 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 01/22] target/hexagon: Use little-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 02/22] target/i386: " Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 03/22] target/riscv: Use little-endian variant of cpu_ld/st_data*() for vector Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 04/22] target/rx: Use little-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 05/22] target/tricore: " Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 06/22] target/hppa: Use big-endian " Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 07/22] target/m68k: " Philippe Mathieu-Daudé
2025-12-05 20:02 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 08/22] target/s390x: " Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 09/22] target/sparc: " Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 10/22] target/sh4: Replace cpu_stl_data() call in OCBI helper Philippe Mathieu-Daudé
2025-12-05 20:03 ` Richard Henderson
2025-12-05 20:06 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 11/22] target/mips: Use big-endian variant of cpu_ld/st_data*() for MSA opcode Philippe Mathieu-Daudé
2025-12-12 16:28 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 12/22] target/mips: Introduce loadu8() & loads4() helpers Philippe Mathieu-Daudé
2025-12-12 16:32 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 13/22] target/mips: Pass MemOpIdx to atomic load helpers Philippe Mathieu-Daudé
2025-12-12 16:33 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 14/22] target/mips: Drop almask argument of HELPER_LD_ATOMIC() macro Philippe Mathieu-Daudé
2025-12-12 16:35 ` Richard Henderson
2025-12-12 16:43 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 15/22] target/mips: Inline cpu_ld*_mmuidx_ra() calls in atomic load helpers Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 16/22] target/mips: Expand HELPER_LD_ATOMIC() Philippe Mathieu-Daudé
2025-12-12 16:46 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 17/22] target/mips: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers Philippe Mathieu-Daudé
2025-12-12 16:55 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 18/22] target/ppc: Inline cpu_ld/st_data_ra() calls in do_hash() Philippe Mathieu-Daudé
2025-12-12 16:57 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 19/22] target/ppc: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers Philippe Mathieu-Daudé
2025-12-12 16:59 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 20/22] target/ppc: Inline cpu_ldl_data_ra() calls in ICBI helper Philippe Mathieu-Daudé
2025-12-12 17:01 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 21/22] target/ppc: Simplify endianness handling in Altivec opcodes Philippe Mathieu-Daudé
2025-12-12 17:02 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 22/22] accel/tcg: Remove non-explicit endian cpu_ld/st*_data*() helpers Philippe Mathieu-Daudé
2025-11-26 20:32 ` Philippe Mathieu-Daudé
2025-12-12 17:02 ` Richard Henderson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).