From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-s390x@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-riscv@nongnu.org, qemu-ppc@nongnu.org,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Helge Deller" <deller@gmx.de>
Subject: [PATCH-for-11.0 v3 06/22] target/hppa: Use big-endian variant of cpu_ld/st_data*()
Date: Wed, 26 Nov 2025 21:21:42 +0100 [thread overview]
Message-ID: <20251126202200.23100-7-philmd@linaro.org> (raw)
In-Reply-To: <20251126202200.23100-1-philmd@linaro.org>
We only build the HPPA target using big endianness order,
therefore the cpu_ld/st_data*() definitions expand to the big
endian declarations. Use the explicit big-endian variants.
Mechanical change running:
$ tgt=hppa; \
end=be; \
for op in data mmuidx_ra; do \
for ac in uw sw l q; do \
sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
for ac in w l q; do \
sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
$(git grep -l cpu_ target/${tgt}/); \
done;
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/op_helper.c | 44 ++++++++++++++++++++---------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index 0458378abb2..65faf03cd0a 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -107,7 +107,7 @@ static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong val,
cpu_stb_data_ra(env, addr, val, ra);
break;
case 2:
- cpu_stw_data_ra(env, addr, val, ra);
+ cpu_stw_be_data_ra(env, addr, val, ra);
break;
case 1:
/* The 3 byte store must appear atomic. */
@@ -115,11 +115,11 @@ static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong val,
atomic_store_mask32(env, addr, val, 0x00ffffffu, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 16, ra);
- cpu_stw_data_ra(env, addr + 1, val, ra);
+ cpu_stw_be_data_ra(env, addr + 1, val, ra);
}
break;
default:
- cpu_stl_data_ra(env, addr, val, ra);
+ cpu_stl_be_data_ra(env, addr, val, ra);
break;
}
}
@@ -132,7 +132,7 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
cpu_stb_data_ra(env, addr, val, ra);
break;
case 6:
- cpu_stw_data_ra(env, addr, val, ra);
+ cpu_stw_be_data_ra(env, addr, val, ra);
break;
case 5:
/* The 3 byte store must appear atomic. */
@@ -140,11 +140,11 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask32(env, addr, val, 0x00ffffffu, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 16, ra);
- cpu_stw_data_ra(env, addr + 1, val, ra);
+ cpu_stw_be_data_ra(env, addr + 1, val, ra);
}
break;
case 4:
- cpu_stl_data_ra(env, addr, val, ra);
+ cpu_stl_be_data_ra(env, addr, val, ra);
break;
case 3:
/* The 5 byte store must appear atomic. */
@@ -152,7 +152,7 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask64(env, addr, val, 0x000000ffffffffffull, 5, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 32, ra);
- cpu_stl_data_ra(env, addr + 1, val, ra);
+ cpu_stl_be_data_ra(env, addr + 1, val, ra);
}
break;
case 2:
@@ -160,8 +160,8 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
if (parallel) {
atomic_store_mask64(env, addr, val, 0x0000ffffffffffffull, 6, ra);
} else {
- cpu_stw_data_ra(env, addr, val >> 32, ra);
- cpu_stl_data_ra(env, addr + 2, val, ra);
+ cpu_stw_be_data_ra(env, addr, val >> 32, ra);
+ cpu_stl_be_data_ra(env, addr + 2, val, ra);
}
break;
case 1:
@@ -170,12 +170,12 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask64(env, addr, val, 0x00ffffffffffffffull, 7, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 48, ra);
- cpu_stw_data_ra(env, addr + 1, val >> 32, ra);
- cpu_stl_data_ra(env, addr + 3, val, ra);
+ cpu_stw_be_data_ra(env, addr + 1, val >> 32, ra);
+ cpu_stl_be_data_ra(env, addr + 3, val, ra);
}
break;
default:
- cpu_stq_data_ra(env, addr, val, ra);
+ cpu_stq_be_data_ra(env, addr, val, ra);
break;
}
}
@@ -211,12 +211,12 @@ static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong val,
if (parallel) {
atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra);
} else {
- cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
+ cpu_stw_be_data_ra(env, addr - 3, val >> 16, ra);
cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
}
break;
case 2:
- cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
+ cpu_stw_be_data_ra(env, addr - 2, val >> 16, ra);
break;
case 1:
cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
@@ -239,8 +239,8 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask64(env, addr - 7, val,
0xffffffffffffff00ull, 7, ra);
} else {
- cpu_stl_data_ra(env, addr - 7, val >> 32, ra);
- cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
+ cpu_stl_be_data_ra(env, addr - 7, val >> 32, ra);
+ cpu_stw_be_data_ra(env, addr - 3, val >> 16, ra);
cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
}
break;
@@ -250,8 +250,8 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask64(env, addr - 6, val,
0xffffffffffff0000ull, 6, ra);
} else {
- cpu_stl_data_ra(env, addr - 6, val >> 32, ra);
- cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
+ cpu_stl_be_data_ra(env, addr - 6, val >> 32, ra);
+ cpu_stw_be_data_ra(env, addr - 2, val >> 16, ra);
}
break;
case 5:
@@ -260,24 +260,24 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val,
atomic_store_mask64(env, addr - 5, val,
0xffffffffff000000ull, 5, ra);
} else {
- cpu_stl_data_ra(env, addr - 5, val >> 32, ra);
+ cpu_stl_be_data_ra(env, addr - 5, val >> 32, ra);
cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
}
break;
case 4:
- cpu_stl_data_ra(env, addr - 4, val >> 32, ra);
+ cpu_stl_be_data_ra(env, addr - 4, val >> 32, ra);
break;
case 3:
/* The 3 byte store must appear atomic. */
if (parallel) {
atomic_store_mask32(env, addr - 3, val >> 32, 0xffffff00u, ra);
} else {
- cpu_stw_data_ra(env, addr - 3, val >> 48, ra);
+ cpu_stw_be_data_ra(env, addr - 3, val >> 48, ra);
cpu_stb_data_ra(env, addr - 1, val >> 40, ra);
}
break;
case 2:
- cpu_stw_data_ra(env, addr - 2, val >> 48, ra);
+ cpu_stw_be_data_ra(env, addr - 2, val >> 48, ra);
break;
case 1:
cpu_stb_data_ra(env, addr - 1, val >> 56, ra);
--
2.51.0
next prev parent reply other threads:[~2025-11-26 20:23 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-26 20:21 [PATCH-for-11.0 v3 00/22] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data() Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 01/22] target/hexagon: Use little-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 02/22] target/i386: " Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 03/22] target/riscv: Use little-endian variant of cpu_ld/st_data*() for vector Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 04/22] target/rx: Use little-endian variant of cpu_ld/st_data*() Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 05/22] target/tricore: " Philippe Mathieu-Daudé
2025-11-26 20:21 ` Philippe Mathieu-Daudé [this message]
2025-11-26 20:21 ` [PATCH-for-11.0 v3 07/22] target/m68k: Use big-endian " Philippe Mathieu-Daudé
2025-12-05 20:02 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 08/22] target/s390x: " Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 09/22] target/sparc: " Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 10/22] target/sh4: Replace cpu_stl_data() call in OCBI helper Philippe Mathieu-Daudé
2025-12-05 20:03 ` Richard Henderson
2025-12-05 20:06 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 11/22] target/mips: Use big-endian variant of cpu_ld/st_data*() for MSA opcode Philippe Mathieu-Daudé
2025-12-12 16:28 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 12/22] target/mips: Introduce loadu8() & loads4() helpers Philippe Mathieu-Daudé
2025-12-12 16:32 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 13/22] target/mips: Pass MemOpIdx to atomic load helpers Philippe Mathieu-Daudé
2025-12-12 16:33 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 14/22] target/mips: Drop almask argument of HELPER_LD_ATOMIC() macro Philippe Mathieu-Daudé
2025-12-12 16:35 ` Richard Henderson
2025-12-12 16:43 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 15/22] target/mips: Inline cpu_ld*_mmuidx_ra() calls in atomic load helpers Philippe Mathieu-Daudé
2025-11-26 20:21 ` [PATCH-for-11.0 v3 16/22] target/mips: Expand HELPER_LD_ATOMIC() Philippe Mathieu-Daudé
2025-12-12 16:46 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 17/22] target/mips: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers Philippe Mathieu-Daudé
2025-12-12 16:55 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 18/22] target/ppc: Inline cpu_ld/st_data_ra() calls in do_hash() Philippe Mathieu-Daudé
2025-12-12 16:57 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 19/22] target/ppc: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers Philippe Mathieu-Daudé
2025-12-12 16:59 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 20/22] target/ppc: Inline cpu_ldl_data_ra() calls in ICBI helper Philippe Mathieu-Daudé
2025-12-12 17:01 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 21/22] target/ppc: Simplify endianness handling in Altivec opcodes Philippe Mathieu-Daudé
2025-12-12 17:02 ` Richard Henderson
2025-11-26 20:21 ` [PATCH-for-11.0 v3 22/22] accel/tcg: Remove non-explicit endian cpu_ld/st*_data*() helpers Philippe Mathieu-Daudé
2025-11-26 20:32 ` Philippe Mathieu-Daudé
2025-12-12 17:02 ` Richard Henderson
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