From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D661D116F3 for ; Mon, 1 Dec 2025 01:45:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vPsx9-0001iX-1n; Sun, 30 Nov 2025 20:43:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vPsx3-0001ex-Tb; Sun, 30 Nov 2025 20:43:42 -0500 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vPswv-0004os-O1; Sun, 30 Nov 2025 20:43:41 -0500 Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5B11h2bu056810 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 1 Dec 2025 09:43:02 +0800 (+08) (envelope-from alvinga@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 1 Dec 2025 09:43:02 +0800 To: , CC: , , , , , , Alvin Chang , Yu-Ming Chang Subject: [PATCH v3 1/2] target/riscv: Add "debug-1.0" to specify debug specification v1.0 Date: Mon, 1 Dec 2025 09:42:54 +0800 Message-ID: <20251201014255.230069-2-alvinga@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251201014255.230069-1-alvinga@andestech.com> References: <20251201014255.230069-1-alvinga@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.0.15.183] X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 5B11h2bu056810 Received-SPF: pass client-ip=60.248.80.70; envelope-from=alvinga@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_DYNAMIC=0.982, SPF_PASS=-0.001, TVD_RCVD_IP=0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Alvin Chang From: Alvin Chang via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently RISC-V CPU has a property "debug" which is equivalent to old debug specification v0.13 version. Now we have ratified debug specification v1.0 version. To support both versions, we add "debug-1.0" as one of RISC-V CPU property to let user specify that debug v0.13 or debug v1.0 is enabled. When debug-1.0=false CPU fallbacks to default v0.13 version. Note that "debug-1.0" depends on "debug" property ("debug" is default true). Take "max" for example, the possible settings are: * -cpu max --> debug v0.13 is default enabled * -cpu max,debug=false --> debug is disabled * -cpu max,debug-1.0=true --> debug is enabled and the version is v1.0 Signed-off-by: Alvin Chang Reviewed-by: Yu-Ming Chang Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg_fields.h.inc | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 73d4280..082035b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2637,6 +2637,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { static const Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + DEFINE_PROP_BOOL("debug-1.0", RISCVCPU, cfg.debug_1_00, false), {.name = "pmu-mask", .info = &prop_pmu_mask}, {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */ diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc index a154ecd..402b255 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -151,6 +151,7 @@ BOOL_FIELD(ext_XVentanaCondOps) BOOL_FIELD(mmu) BOOL_FIELD(pmp) BOOL_FIELD(debug) +BOOL_FIELD(debug_1_00) BOOL_FIELD(misa_w) BOOL_FIELD(short_isa_string) -- 2.43.0