From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org, peter.maydell@linaro.org
Subject: [PATCH 1/2] tcg/tci: Introduce INDEX_op_tci_qemu_{ld,st}_rrr
Date: Mon, 1 Dec 2025 17:12:26 -0800 [thread overview]
Message-ID: <20251202011228.503007-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20251202011228.503007-1-richard.henderson@linaro.org>
Since d182123974c4, the number of bits in a MemOpIdx
tops out at 17. This fixes an assert in tcg_out_op_rrm.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 19 +++++++++++++++++++
tcg/tci/tcg-target-opc.h.inc | 2 ++
tcg/tci/tcg-target.c.inc | 14 ++++++++++++--
3 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 700e672616..e15d4e8e08 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -794,12 +794,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
taddr = regs[r1];
regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr);
break;
+ case INDEX_op_tci_qemu_ld_rrr:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ taddr = regs[r1];
+ oi = regs[r2];
+ regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr);
+ break;
case INDEX_op_qemu_st:
tci_args_rrm(insn, &r0, &r1, &oi);
taddr = regs[r1];
tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr);
break;
+ case INDEX_op_tci_qemu_st_rrr:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ taddr = regs[r1];
+ oi = regs[r2];
+ tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr);
+ break;
case INDEX_op_qemu_ld2:
tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
@@ -1050,6 +1062,13 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
op_name, str_r(r0), str_r(r1), oi);
break;
+ case INDEX_op_tci_qemu_ld_rrr:
+ case INDEX_op_tci_qemu_st_rrr:
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ info->fprintf_func(info->stream, "%-12s %s, %s, %s",
+ op_name, str_r(r0), str_r(r1), str_r(r2));
+ break;
+
case INDEX_op_qemu_ld2:
case INDEX_op_qemu_st2:
tci_args_rrrr(insn, &r0, &r1, &r2, &r3);
diff --git a/tcg/tci/tcg-target-opc.h.inc b/tcg/tci/tcg-target-opc.h.inc
index 4eb32ed736..f8bfffc125 100644
--- a/tcg/tci/tcg-target-opc.h.inc
+++ b/tcg/tci/tcg-target-opc.h.inc
@@ -13,3 +13,5 @@ DEF(tci_rotl32, 1, 2, 0, TCG_OPF_NOT_PRESENT)
DEF(tci_rotr32, 1, 2, 0, TCG_OPF_NOT_PRESENT)
DEF(tci_setcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT)
DEF(tci_movcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT)
+DEF(tci_qemu_ld_rrr, 1, 2, 0, TCG_OPF_NOT_PRESENT)
+DEF(tci_qemu_st_rrr, 0, 3, 0, TCG_OPF_NOT_PRESENT)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 35c66a4836..532f87262c 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -1188,7 +1188,12 @@ static const TCGOutOpStore outop_st = {
static void tgen_qemu_ld(TCGContext *s, TCGType type, TCGReg data,
TCGReg addr, MemOpIdx oi)
{
- tcg_out_op_rrm(s, INDEX_op_qemu_ld, data, addr, oi);
+ if (oi & ~0xffff) {
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, oi);
+ tcg_out_op_rrr(s, INDEX_op_tci_qemu_ld_rrr, data, addr, TCG_REG_TMP);
+ } else {
+ tcg_out_op_rrm(s, INDEX_op_qemu_ld, data, addr, oi);
+ }
}
static const TCGOutOpQemuLdSt outop_qemu_ld = {
@@ -1213,7 +1218,12 @@ static const TCGOutOpQemuLdSt2 outop_qemu_ld2 = {
static void tgen_qemu_st(TCGContext *s, TCGType type, TCGReg data,
TCGReg addr, MemOpIdx oi)
{
- tcg_out_op_rrm(s, INDEX_op_qemu_st, data, addr, oi);
+ if (oi & ~0xffff) {
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, oi);
+ tcg_out_op_rrr(s, INDEX_op_tci_qemu_st_rrr, data, addr, TCG_REG_TMP);
+ } else {
+ tcg_out_op_rrm(s, INDEX_op_qemu_st, data, addr, oi);
+ }
}
static const TCGOutOpQemuLdSt outop_qemu_st = {
--
2.43.0
next prev parent reply other threads:[~2025-12-02 1:13 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-02 1:12 [PATCH 0/2] TCI fixes Richard Henderson
2025-12-02 1:12 ` Richard Henderson [this message]
2025-12-02 18:06 ` [PATCH 1/2] tcg/tci: Introduce INDEX_op_tci_qemu_{ld,st}_rrr Philippe Mathieu-Daudé
2025-12-02 18:47 ` Philippe Mathieu-Daudé
2025-12-02 1:12 ` [PATCH 2/2] tcg: Zero extend 32-bit addresses for TCI Richard Henderson
2025-12-02 19:58 ` Philippe Mathieu-Daudé
2025-12-02 21:10 ` Richard Henderson
2025-12-02 11:55 ` [PATCH 0/2] TCI fixes Alex Bennée
2025-12-02 19:55 ` [PATCH 1.5/2] tcg: Move maybe_{extend, free}_addr64() functions around Philippe Mathieu-Daudé
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