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([2a10:d582:31e:0:d0df:e484:1145:883f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4790b0e21e8sm381169835e9.15.2025.12.02.04.02.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Dec 2025 04:02:53 -0800 (PST) From: Jim MacArthur To: qemu-devel@nongnu.org Cc: Jim MacArthur Subject: [PATCH V4 3/4] target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max Date: Tue, 2 Dec 2025 12:00:40 +0000 Message-ID: <20251202120250.763150-4-jim.macarthur@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251202120250.763150-1-jim.macarthur@linaro.org> References: <20251202120250.763150-1-jim.macarthur@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org docs/system/arm/emulation.rst: Add ASID2 Signed-off-by: Jim MacArthur --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 31a5878a8f..3f30ea5a30 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -24,6 +24,7 @@ the following architecture extensions: - FEAT_AIE (Memory Attribute Index Enhancement) - FEAT_Armv9_Crypto (Armv9 Cryptographic Extension) - FEAT_ASID16 (16 bit ASID) +- FEAT_ASID2 (Concurrent use of two ASIDs) - FEAT_ATS1A (Address Translation operations that ignore stage 1 permissions) - FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 6871956382..ef4c0c8d73 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1334,6 +1334,10 @@ void aarch64_max_tcg_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* FEAT_AIE */ SET_IDREG(isar, ID_AA64MMFR3, t); + t = GET_IDREG(isar, ID_AA64MMFR4); + t = FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* FEAT_ASID2 */ + SET_IDREG(isar, ID_AA64MMFR4, t); + t = GET_IDREG(isar, ID_AA64ZFR0); t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ -- 2.43.0