From: Jim MacArthur <jim.macarthur@linaro.org>
To: qemu-devel@nongnu.org
Cc: Jim MacArthur <jim.macarthur@linaro.org>
Subject: [PATCH V5 0/4] Basic ASID2 support
Date: Thu, 4 Dec 2025 18:04:10 +0000 [thread overview]
Message-ID: <20251204180617.1190660-1-jim.macarthur@linaro.org> (raw)
Thanks to Gustavo Romero for reviews.
Changes in v5:
- Patch 2:
- TLB flush when A2/FNG0/FNG1 could be written to.
- Patch 4:
- SPDX License identifier moved to first line.
Jim MacArthur (4):
target/arm: Enable ID_AA64MMFR4_EL1 register
target/arm: Allow writes to FNG1, FNG0, A2
target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max
tests: Add test for ASID2 and write/read of feature bits
docs/system/arm/emulation.rst | 1 +
target/arm/cpu-features.h | 7 +++
target/arm/cpu-sysregs.h.inc | 1 +
target/arm/helper.c | 22 ++++++++-
target/arm/tcg/cpu64.c | 4 ++
tests/tcg/aarch64/system/asid2.c | 76 ++++++++++++++++++++++++++++++++
6 files changed, 109 insertions(+), 2 deletions(-)
create mode 100644 tests/tcg/aarch64/system/asid2.c
--
2.43.0
next reply other threads:[~2025-12-04 18:07 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-04 18:04 Jim MacArthur [this message]
2025-12-04 18:04 ` [PATCH 1/4] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur
2025-12-04 18:04 ` [PATCH 2/4] target/arm: Allow writes to FNG1, FNG0, A2 Jim MacArthur
2025-12-05 15:30 ` Richard Henderson
2025-12-09 15:04 ` Jim MacArthur
2025-12-09 15:39 ` Richard Henderson
2025-12-04 18:04 ` [PATCH 3/4] target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max Jim MacArthur
2025-12-04 18:04 ` [PATCH 4/4] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur
2025-12-04 18:30 ` [PATCH V5 0/4] Basic ASID2 support Alex Bennée
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