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([172.56.17.137]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-88830bfc22dsm21591636d6.43.2025.12.05.08.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Dec 2025 08:20:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 2/6] tcg/tci: Introduce INDEX_op_tci_qemu_{ld,st}_rrr Date: Fri, 5 Dec 2025 10:20:03 -0600 Message-ID: <20251205162007.26405-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251205162007.26405-1-richard.henderson@linaro.org> References: <20251205162007.26405-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::736; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x736.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Since d182123974c4, the number of bits in a MemOpIdx tops out at 17. which won't fit in the TCI rrm format, thus an assertion failure. Introduce new opcodes that take the MemOpIdx from a register, as we already do for qemu_ld2 and qemu_st2. Fixes: d182123974c4 ("include/exec/memopidx: Adjust for 32 mmu indexes") Tested-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 19 +++++++++++++++++++ tcg/tci/tcg-target-opc.h.inc | 2 ++ tcg/tci/tcg-target.c.inc | 14 ++++++++++++-- 3 files changed, 33 insertions(+), 2 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 700e672616..e15d4e8e08 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -794,12 +794,24 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, taddr = regs[r1]; regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr); break; + case INDEX_op_tci_qemu_ld_rrr: + tci_args_rrr(insn, &r0, &r1, &r2); + taddr = regs[r1]; + oi = regs[r2]; + regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr); + break; case INDEX_op_qemu_st: tci_args_rrm(insn, &r0, &r1, &oi); taddr = regs[r1]; tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); break; + case INDEX_op_tci_qemu_st_rrr: + tci_args_rrr(insn, &r0, &r1, &r2); + taddr = regs[r1]; + oi = regs[r2]; + tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); + break; case INDEX_op_qemu_ld2: tcg_debug_assert(TCG_TARGET_REG_BITS == 32); @@ -1050,6 +1062,13 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) op_name, str_r(r0), str_r(r1), oi); break; + case INDEX_op_tci_qemu_ld_rrr: + case INDEX_op_tci_qemu_st_rrr: + tci_args_rrr(insn, &r0, &r1, &r2); + info->fprintf_func(info->stream, "%-12s %s, %s, %s", + op_name, str_r(r0), str_r(r1), str_r(r2)); + break; + case INDEX_op_qemu_ld2: case INDEX_op_qemu_st2: tci_args_rrrr(insn, &r0, &r1, &r2, &r3); diff --git a/tcg/tci/tcg-target-opc.h.inc b/tcg/tci/tcg-target-opc.h.inc index 4eb32ed736..f8bfffc125 100644 --- a/tcg/tci/tcg-target-opc.h.inc +++ b/tcg/tci/tcg-target-opc.h.inc @@ -13,3 +13,5 @@ DEF(tci_rotl32, 1, 2, 0, TCG_OPF_NOT_PRESENT) DEF(tci_rotr32, 1, 2, 0, TCG_OPF_NOT_PRESENT) DEF(tci_setcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT) DEF(tci_movcond32, 1, 2, 1, TCG_OPF_NOT_PRESENT) +DEF(tci_qemu_ld_rrr, 1, 2, 0, TCG_OPF_NOT_PRESENT) +DEF(tci_qemu_st_rrr, 0, 3, 0, TCG_OPF_NOT_PRESENT) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 35c66a4836..532f87262c 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -1188,7 +1188,12 @@ static const TCGOutOpStore outop_st = { static void tgen_qemu_ld(TCGContext *s, TCGType type, TCGReg data, TCGReg addr, MemOpIdx oi) { - tcg_out_op_rrm(s, INDEX_op_qemu_ld, data, addr, oi); + if (oi & ~0xffff) { + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, oi); + tcg_out_op_rrr(s, INDEX_op_tci_qemu_ld_rrr, data, addr, TCG_REG_TMP); + } else { + tcg_out_op_rrm(s, INDEX_op_qemu_ld, data, addr, oi); + } } static const TCGOutOpQemuLdSt outop_qemu_ld = { @@ -1213,7 +1218,12 @@ static const TCGOutOpQemuLdSt2 outop_qemu_ld2 = { static void tgen_qemu_st(TCGContext *s, TCGType type, TCGReg data, TCGReg addr, MemOpIdx oi) { - tcg_out_op_rrm(s, INDEX_op_qemu_st, data, addr, oi); + if (oi & ~0xffff) { + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, oi); + tcg_out_op_rrr(s, INDEX_op_tci_qemu_st_rrr, data, addr, TCG_REG_TMP); + } else { + tcg_out_op_rrm(s, INDEX_op_qemu_st, data, addr, oi); + } } static const TCGOutOpQemuLdSt outop_qemu_st = { -- 2.43.0