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From: Aditya Gupta <adityag@linux.ibm.com>
To: <qemu-devel@nongnu.org>
Cc: <qemu-ppc@nongnu.org>, Hari Bathini <hbathini@linux.ibm.com>,
	Sourabh Jain <sourabhjain@linux.ibm.com>,
	Harsh Prateek Bora <harshpb@linux.ibm.com>
Subject: [PATCH v2 0/9] Implement MPIPL for PowerNV
Date: Sat,  6 Dec 2025 11:26:39 +0530	[thread overview]
Message-ID: <20251206055648.1908734-1-adityag@linux.ibm.com> (raw)

Overview
=========

Implemented MPIPL (Memory Preserving IPL, aka fadump) on PowerNV machine
in QEMU.

Note: It's okay if this isn't merged as there might be less users. Sending
for archieval purpose, as the patches can be referred for how fadump/mpipl
can be implemented in baremetal/PowerNV/any other arch QEMU.

Fadump is an alternative dump mechanism to kdump, in which we the firmware
does a memory preserving boot, and the second/crashkernel is booted fresh
like a normal system reset, instead of the crashed kernel loading the
second/crashkernel in case of kdump.

MPIPL in PowerNV, is similar to fadump in Pseries. The idea is same, memory
preserving, where in PowerNV we are assisted by SBE (Self Boot Engine) &
Hostboot, while in Pseries we are assisted by PHyp (Power Hypervisor)

For implementing in baremetal/powernv QEMU, we need to export a
"ibm,opal/dump" node in the device tree, to tell the kernel we support
MPIPL

Once kernel sees the support, and "fadump=on" is passed on commandline,
kernel will register memory regions to preserve with Skiboot.

Kernel sends these data using OPAL calls, after which skiboot/opal saves
the memory region details to MDST and MDDT tables (S-source, D-destination)

Skiboot then triggers the "S0 Interrupt" to the SBE (Self Boot Engine),
along with OPAL's relocated base address.

SBE then stops all core clocks, and only does particular ISteps for a
memory preserving boot.

Then, hostboot comes up, and with help of the relocated base address, it
accesses MDST & MDDT tables (S-source and D-destination), and preserves the
memory regions according to the data in these tables.
And after preserving, it writes the preserved memory region details to MDRT
tables (R-Result), for the kernel to know where/whether a memory region is
preserved.

Both SBE's and hostboot responsiblities have in implemented in the SBE code
in QEMU.

Then in the second kernel/crashkernel boot, OPAL passes the "mpipl-boot"
property for the kernel to know that a dump is active, which kernel then
exports in /proc/vmcore

Git Tree for Testing
====================

https://github.com/adi-g15-ibm/qemu/tree/fadump-powernv-v2

Aditya Gupta (9):
  hw/ppc: Move SBE host doorbell function to top of file
  hw/ppc: Implement S0 SBE interrupt as cpu_pause then host reset
  hw/ppc: Handle stash command in PowerNV SBE
  pnv/mpipl: Preserve memory regions as per MDST/MDDT tables
  pnv/mpipl: Preserve CPU registers after crash
  pnv/mpipl: Set thread entry size to be allocated by firmware
  pnv/mpipl: Write the preserved CPU and MDRT state
  pnv/mpipl: Enable MPIPL support
  tests/functional: Add test for MPIPL in PowerNV

 hw/ppc/meson.build                    |   1 +
 hw/ppc/pnv.c                          |  90 ++++++
 hw/ppc/pnv_mpipl.c                    | 388 ++++++++++++++++++++++++++
 hw/ppc/pnv_sbe.c                      |  74 ++++-
 include/hw/ppc/pnv.h                  |   7 +
 include/hw/ppc/pnv_mpipl.h            | 167 +++++++++++
 tests/functional/ppc64/test_fadump.py |  35 +--
 7 files changed, 731 insertions(+), 31 deletions(-)
 create mode 100644 hw/ppc/pnv_mpipl.c
 create mode 100644 include/hw/ppc/pnv_mpipl.h

-- 
2.52.0



             reply	other threads:[~2025-12-06  5:59 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-06  5:56 Aditya Gupta [this message]
2025-12-06  5:56 ` [PATCH v2 1/9] hw/ppc: Move SBE host doorbell function to top of file Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 2/9] hw/ppc: Implement S0 SBE interrupt as cpu_pause then host reset Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 3/9] hw/ppc: Handle stash command in PowerNV SBE Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 4/9] pnv/mpipl: Preserve memory regions as per MDST/MDDT tables Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 5/9] pnv/mpipl: Preserve CPU registers after crash Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 6/9] pnv/mpipl: Set thread entry size to be allocated by firmware Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 7/9] pnv/mpipl: Write the preserved CPU and MDRT state Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 8/9] pnv/mpipl: Enable MPIPL support Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 9/9] tests/functional: Add test for MPIPL in PowerNV Aditya Gupta

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