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From: Aditya Gupta <adityag@linux.ibm.com>
To: <qemu-devel@nongnu.org>
Cc: <qemu-ppc@nongnu.org>, Hari Bathini <hbathini@linux.ibm.com>,
	Sourabh Jain <sourabhjain@linux.ibm.com>,
	Harsh Prateek Bora <harshpb@linux.ibm.com>
Subject: [PATCH v2 1/9] hw/ppc: Move SBE host doorbell function to top of file
Date: Sat,  6 Dec 2025 11:26:40 +0530	[thread overview]
Message-ID: <20251206055648.1908734-2-adityag@linux.ibm.com> (raw)
In-Reply-To: <20251206055648.1908734-1-adityag@linux.ibm.com>

Moved 'pnv_sbe_set_host_doorbell' as-it-is to above
'pnv_sbe_power9_xscom_ctrl_write'.

This is done since in a future patch, S0 interrupt implementation uses
'pnv_sbe_set_host_doorbell', hence the host doorbell function needs to
be declared/defined before 'pnv_sbe_power9_xscom_ctrl_write' where we
implement the S0 interrupt.

No functional change.

Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
 hw/ppc/pnv_sbe.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
index 34dc013d47bb..b9b28c5deaef 100644
--- a/hw/ppc/pnv_sbe.c
+++ b/hw/ppc/pnv_sbe.c
@@ -80,6 +80,15 @@
 #define SBE_CONTROL_REG_S0              PPC_BIT(14)
 #define SBE_CONTROL_REG_S1              PPC_BIT(15)
 
+static void pnv_sbe_set_host_doorbell(PnvSBE *sbe, uint64_t val)
+{
+    val &= SBE_HOST_RESPONSE_MASK; /* Is this right? What does HW do? */
+    sbe->host_doorbell = val;
+
+    trace_pnv_sbe_reg_set_host_doorbell(val);
+    qemu_set_irq(sbe->psi_irq, !!val);
+}
+
 struct sbe_msg {
     uint64_t reg[4];
 };
@@ -125,15 +134,6 @@ static const MemoryRegionOps pnv_sbe_power9_xscom_ctrl_ops = {
     .endianness = DEVICE_BIG_ENDIAN,
 };
 
-static void pnv_sbe_set_host_doorbell(PnvSBE *sbe, uint64_t val)
-{
-    val &= SBE_HOST_RESPONSE_MASK; /* Is this right? What does HW do? */
-    sbe->host_doorbell = val;
-
-    trace_pnv_sbe_reg_set_host_doorbell(val);
-    qemu_set_irq(sbe->psi_irq, !!val);
-}
-
 /* SBE Target Type */
 #define SBE_TARGET_TYPE_PROC            0x00
 #define SBE_TARGET_TYPE_EX              0x01
-- 
2.52.0



  reply	other threads:[~2025-12-06  5:59 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-06  5:56 [PATCH v2 0/9] Implement MPIPL for PowerNV Aditya Gupta
2025-12-06  5:56 ` Aditya Gupta [this message]
2025-12-06  5:56 ` [PATCH v2 2/9] hw/ppc: Implement S0 SBE interrupt as cpu_pause then host reset Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 3/9] hw/ppc: Handle stash command in PowerNV SBE Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 4/9] pnv/mpipl: Preserve memory regions as per MDST/MDDT tables Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 5/9] pnv/mpipl: Preserve CPU registers after crash Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 6/9] pnv/mpipl: Set thread entry size to be allocated by firmware Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 7/9] pnv/mpipl: Write the preserved CPU and MDRT state Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 8/9] pnv/mpipl: Enable MPIPL support Aditya Gupta
2025-12-06  5:56 ` [PATCH v2 9/9] tests/functional: Add test for MPIPL in PowerNV Aditya Gupta

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