From: Aditya Gupta <adityag@linux.ibm.com>
To: <qemu-devel@nongnu.org>
Cc: <qemu-ppc@nongnu.org>, Hari Bathini <hbathini@linux.ibm.com>,
Sourabh Jain <sourabhjain@linux.ibm.com>,
Harsh Prateek Bora <harshpb@linux.ibm.com>
Subject: [PATCH v2 3/9] hw/ppc: Handle stash command in PowerNV SBE
Date: Sat, 6 Dec 2025 11:26:42 +0530 [thread overview]
Message-ID: <20251206055648.1908734-4-adityag@linux.ibm.com> (raw)
In-Reply-To: <20251206055648.1908734-1-adityag@linux.ibm.com>
Earlier since the SBE_CMD_STASH_MPIPL_CONFIG command was not handled, so
skiboot used to not get any response from SBE:
[ 106.350742821,3] SBE: Message timeout [chip id = 0], cmd = d7, subcmd = 7
[ 106.352067746,3] SBE: Failed to send stash MPIPL config [chip id = 0x0, rc = 254]
Fix this by handling the command in PowerNV SBE, and sending a response so
skiboot knows SBE has handled the STASH command
The stashed skiboot base is later used to access the relocated MDST/MDDT
tables when MPIPL is implemented.
The purpose of stashing relocated base address is explained in following
skiboot commit:
author Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Fri Jul 12 16:47:51 2019 +0530
committer Oliver O'Halloran <oohall@gmail.com> Thu Aug 15 17:53:39 2019 +1000
SBE: Send OPAL relocated base address to SBE
OPAL relocates itself during boot. During memory preserving IPL hostboot needs
to access relocated OPAL base address to get MDST, MDDT tables. Hence send
relocated base address to SBE via 'stash MPIPL config' chip-op. During next
IPL SBE will send stashed data to hostboot... so that hostboot can access
these data.
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/pnv_sbe.c | 27 +++++++++++++++++++++++++++
include/hw/ppc/pnv_mpipl.h | 3 +++
2 files changed, 30 insertions(+)
diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
index d004b7d5c225..af888126e758 100644
--- a/hw/ppc/pnv_sbe.c
+++ b/hw/ppc/pnv_sbe.c
@@ -233,6 +233,7 @@ static void sbe_timer(void *opaque)
static void do_sbe_msg(PnvSBE *sbe)
{
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
struct sbe_msg msg;
uint16_t cmd, ctrl_flags, seq_id;
int i;
@@ -265,6 +266,32 @@ static void do_sbe_msg(PnvSBE *sbe)
timer_del(sbe->timer);
}
break;
+ case SBE_CMD_STASH_MPIPL_CONFIG:
+ /* key = sbe->mbox[1] */
+ switch (sbe->mbox[1]) {
+ case SBE_STASH_KEY_SKIBOOT_BASE:
+ pnv->mpipl_state.skiboot_base = sbe->mbox[2];
+ qemu_log_mask(LOG_UNIMP,
+ "Stashing skiboot base: 0x%" HWADDR_PRIx "\n",
+ pnv->mpipl_state.skiboot_base);
+
+ /*
+ * Set the response register.
+ *
+ * Currently setting the same sequence number in
+ * response as we got in the request.
+ */
+ sbe->mbox[4] = sbe->mbox[0]; /* sequence number */
+ pnv_sbe_set_host_doorbell(sbe,
+ sbe->host_doorbell | SBE_HOST_RESPONSE_WAITING);
+
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP,
+ "SBE: CMD_STASH_MPIPL_CONFIG: Unimplemented key: 0x" TARGET_FMT_lx "\n",
+ sbe->mbox[1]);
+ }
+ break;
default:
qemu_log_mask(LOG_UNIMP, "SBE Unimplemented command: 0x%x\n", cmd);
}
diff --git a/include/hw/ppc/pnv_mpipl.h b/include/hw/ppc/pnv_mpipl.h
index c544984dc76d..60d6ede48209 100644
--- a/include/hw/ppc/pnv_mpipl.h
+++ b/include/hw/ppc/pnv_mpipl.h
@@ -8,11 +8,14 @@
#define PNV_MPIPL_H
#include "qemu/osdep.h"
+#include "exec/hwaddr.h"
typedef struct MpiplPreservedState MpiplPreservedState;
/* Preserved state to be saved in PnvMachineState */
struct MpiplPreservedState {
+ /* skiboot_base will be valid only after OPAL sends relocated base to SBE */
+ hwaddr skiboot_base;
bool is_next_boot_mpipl;
};
--
2.52.0
next prev parent reply other threads:[~2025-12-06 5:59 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-06 5:56 [PATCH v2 0/9] Implement MPIPL for PowerNV Aditya Gupta
2025-12-06 5:56 ` [PATCH v2 1/9] hw/ppc: Move SBE host doorbell function to top of file Aditya Gupta
2025-12-06 5:56 ` [PATCH v2 2/9] hw/ppc: Implement S0 SBE interrupt as cpu_pause then host reset Aditya Gupta
2025-12-06 5:56 ` Aditya Gupta [this message]
2025-12-06 5:56 ` [PATCH v2 4/9] pnv/mpipl: Preserve memory regions as per MDST/MDDT tables Aditya Gupta
2025-12-06 5:56 ` [PATCH v2 5/9] pnv/mpipl: Preserve CPU registers after crash Aditya Gupta
2025-12-06 5:56 ` [PATCH v2 6/9] pnv/mpipl: Set thread entry size to be allocated by firmware Aditya Gupta
2025-12-06 5:56 ` [PATCH v2 7/9] pnv/mpipl: Write the preserved CPU and MDRT state Aditya Gupta
2025-12-06 5:56 ` [PATCH v2 8/9] pnv/mpipl: Enable MPIPL support Aditya Gupta
2025-12-06 5:56 ` [PATCH v2 9/9] tests/functional: Add test for MPIPL in PowerNV Aditya Gupta
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