From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A2F9D374BD for ; Sat, 6 Dec 2025 05:59:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vRlJp-0004In-MJ; Sat, 06 Dec 2025 00:58:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vRlJV-0004AE-4z; Sat, 06 Dec 2025 00:58:38 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vRlJT-0005YH-DK; Sat, 06 Dec 2025 00:58:36 -0500 Received: from pps.filterd (m0353725.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5B61X8pD014920; Sat, 6 Dec 2025 05:58:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=3bnyjvNVAadL6Npin zBFObLYXXrrBh/m/1IjZafJhp8=; b=kWrDYKSJGSxruf7Ywtq7EyavXCynea2GB 4VvTvdx3WkKS80V3H5uA5gHvo6JRjZmZYvJ78N4cgtoCg5dK/q9MrhLdnxB1AJMF bEFSBnxRPYuKhGG3Y/nxG2kJg1FOeXciCCw1Z/vLsklDXCishaurYZ1g7dDKK1hw 75z2kZBgzODj3SL1XJ7ZVJT5AXQbxQ6tWXtD5IEsTfwmyhU2C8kj8t4Fn+mYI3rj ozFqdN+UKJRp2Tde7SRTVR/h25/VBiKbAqkPrlHE9Ybb13BW9php76vEOD6EeLko zt1+8gzRunEuPUeQsQ+JfREi//NFVSfRfOUeS1pphDLuzglxpzM+Q== Received: from ppma13.dal12v.mail.ibm.com (dd.9e.1632.ip4.static.sl-reverse.com [50.22.158.221]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4avawurk72-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 06 Dec 2025 05:58:33 +0000 (GMT) Received: from pps.filterd (ppma13.dal12v.mail.ibm.com [127.0.0.1]) by ppma13.dal12v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 5B630n4t003834; Sat, 6 Dec 2025 05:58:33 GMT Received: from smtprelay05.fra02v.mail.ibm.com ([9.218.2.225]) by ppma13.dal12v.mail.ibm.com (PPS) with ESMTPS id 4ardck8tb4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 06 Dec 2025 05:58:33 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay05.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 5B65wTIi44826928 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 6 Dec 2025 05:58:29 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 61F8F20043; Sat, 6 Dec 2025 05:58:29 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0F86B20040; Sat, 6 Dec 2025 05:58:27 +0000 (GMT) Received: from li-3c92a0cc-27cf-11b2-a85c-b804d9ca68fa.ibm.com (unknown [9.39.31.93]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Sat, 6 Dec 2025 05:58:26 +0000 (GMT) From: Aditya Gupta To: Cc: , Hari Bathini , Sourabh Jain , Harsh Prateek Bora Subject: [PATCH v2 5/9] pnv/mpipl: Preserve CPU registers after crash Date: Sat, 6 Dec 2025 11:26:44 +0530 Message-ID: <20251206055648.1908734-6-adityag@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251206055648.1908734-1-adityag@linux.ibm.com> References: <20251206055648.1908734-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: cRbts86dwOOE7cKo0kNv6EcFZzAwdyxU X-Proofpoint-ORIG-GUID: cRbts86dwOOE7cKo0kNv6EcFZzAwdyxU X-Authority-Analysis: v=2.4 cv=aY9sXBot c=1 sm=1 tr=0 ts=6933c60a cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=R8Osvl7jfSHEaf5PJVYA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA2MDAwNyBTYWx0ZWRfXzK1+SopYFd6W fuCHwitOpEmpgOwVXesVciUJSdnHw+2iMljwBhBBpXBegb7fIeNbamzUFPxdAQ3RKV86Ppdp9Gc GszmHuaeEUd1qVzWAQEIYosrqU9/5iDzGmwTgolhRl4gUGC+HQlm3ZutYsDX+4xVGdiiHlCa16w 4I5mcyqxy1hN02P3MNRPNRnZNSoWc36zvm6V+o1wCQfYonS9igWBaekOcir6YpzJf1Da6x+7U0d 24hFJDlardDON/TkcgKtBcxljqR/ePpHfsxWHHKMGUAb9TyN4t6CfH/Bh4eRLF8g2ai0JZdasmI YBbSanEMz5aB/M4FDXwsZAk4Oh3JKkS0qSm/M29RN3W3tAtiZl328dLmZ/5a2JXuih5mThfvxah DodxJzUGE/YP6F0RHkK9oCGbhraQpw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-06_01,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512060007 Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Kernel expects the platform to provide CPU registers after pausing execution of the CPUs. Currently only exporting the registers, used by Linux, for generating the /proc/vmcore Signed-off-by: Aditya Gupta --- hw/ppc/pnv_mpipl.c | 102 +++++++++++++++++++++++++++++++++++++ include/hw/ppc/pnv_mpipl.h | 62 ++++++++++++++++++++++ 2 files changed, 164 insertions(+) diff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c index a4f7113a44fd..8b41938c2e87 100644 --- a/hw/ppc/pnv_mpipl.c +++ b/hw/ppc/pnv_mpipl.c @@ -8,6 +8,8 @@ #include "qemu/log.h" #include "qemu/units.h" #include "system/address-spaces.h" +#include "system/cpus.h" +#include "system/hw_accel.h" #include "system/runstate.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_mpipl.h" @@ -17,6 +19,8 @@ (pnv->mpipl_state.skiboot_base + MDST_TABLE_OFF) #define MDDT_TABLE_RELOCATED \ (pnv->mpipl_state.skiboot_base + MDDT_TABLE_OFF) +#define PROC_DUMP_RELOCATED \ + (pnv->mpipl_state.skiboot_base + PROC_DUMP_AREA_OFF) /* * Preserve the memory regions as pointed by MDST table @@ -164,9 +168,107 @@ static bool pnv_mpipl_preserve_mem(PnvMachineState *pnv) return true; } +static void do_store_cpu_regs(CPUState *cpu, MpiplPreservedCPUState *state) +{ + CPUPPCState *env = cpu_env(cpu); + MpiplRegDataHdr *regs_hdr = &state->hdr; + MpiplRegEntry *reg_entries = state->reg_entries; + MpiplRegEntry *curr_reg_entry; + uint32_t num_saved_regs = 0; + + cpu_synchronize_state(cpu); + + regs_hdr->pir = cpu_to_be32(env->spr[SPR_PIR]); + + /* QEMU CPUs are not in Power Saving Mode */ + regs_hdr->core_state = 0xff; + + regs_hdr->off_regentries = 0; + regs_hdr->num_regentries = cpu_to_be32(NUM_REGS_PER_CPU); + + regs_hdr->alloc_size = cpu_to_be32(sizeof(MpiplRegEntry)); + regs_hdr->act_size = cpu_to_be32(sizeof(MpiplRegEntry)); + +#define REG_TYPE_GPR 0x1 +#define REG_TYPE_SPR 0x2 +#define REG_TYPE_TIMA 0x3 + +/* + * ID numbers used by f/w while populating certain registers + * + * Copied these defines from the linux kernel + */ +#define REG_ID_NIP 0x7D0 +#define REG_ID_MSR 0x7D1 +#define REG_ID_CCR 0x7D2 + + curr_reg_entry = reg_entries; + +#define REG_ENTRY(type, num, val) \ + do { \ + curr_reg_entry->reg_type = cpu_to_be32(type); \ + curr_reg_entry->reg_num = cpu_to_be32(num); \ + curr_reg_entry->reg_val = cpu_to_be64(val); \ + ++curr_reg_entry; \ + ++num_saved_regs; \ + } while (0) + + /* Save the GPRs */ + for (int gpr_id = 0; gpr_id < 32; ++gpr_id) { + REG_ENTRY(REG_TYPE_GPR, gpr_id, env->gpr[gpr_id]); + } + + REG_ENTRY(REG_TYPE_SPR, REG_ID_NIP, env->nip); + REG_ENTRY(REG_TYPE_SPR, REG_ID_MSR, env->msr); + + /* + * Ensure the number of registers saved match the number of + * registers per cpu + * + * This will help catch an error if in future a new register entry + * is added/removed while not modifying NUM_PER_CPU_REGS + */ + assert(num_saved_regs == NUM_REGS_PER_CPU); +} + +static void pnv_mpipl_preserve_cpu_state(PnvMachineState *pnv) +{ + MachineState *machine = MACHINE(pnv); + uint32_t num_cpus = machine->smp.cpus; + MpiplPreservedCPUState *state; + CPUState *cpu; + + if (pnv->mpipl_state.cpu_states) { + /* + * CPU States might have been allocated from some past crash, free the + * memory to preven memory leak + */ + g_free(pnv->mpipl_state.cpu_states); + pnv->mpipl_state.num_cpu_states = 0; + } + + pnv->mpipl_state.cpu_states = g_malloc_n(num_cpus, + sizeof(MpiplPreservedCPUState)); + pnv->mpipl_state.num_cpu_states = num_cpus; + + state = pnv->mpipl_state.cpu_states; + + /* Preserve the Processor Dump Area */ + cpu_physical_memory_read(PROC_DUMP_RELOCATED, &pnv->mpipl_state.proc_area, + sizeof(MpiplProcDumpArea)); + + CPU_FOREACH(cpu) { + do_store_cpu_regs(cpu, state); + ++state; + } +} + void do_mpipl_preserve(PnvMachineState *pnv) { + pause_all_vcpus(); + pnv_mpipl_preserve_mem(pnv); + pnv_mpipl_preserve_cpu_state(pnv); /* Mark next boot as Memory-preserving boot */ pnv->mpipl_state.is_next_boot_mpipl = true; diff --git a/include/hw/ppc/pnv_mpipl.h b/include/hw/ppc/pnv_mpipl.h index ec173ba8268e..d85970bba039 100644 --- a/include/hw/ppc/pnv_mpipl.h +++ b/include/hw/ppc/pnv_mpipl.h @@ -16,6 +16,12 @@ typedef struct MdstTableEntry MdstTableEntry; typedef struct MdrtTableEntry MdrtTableEntry; typedef struct MpiplPreservedState MpiplPreservedState; +typedef struct MpiplRegDataHdr MpiplRegDataHdr; +typedef struct MpiplRegEntry MpiplRegEntry; +typedef struct MpiplProcDumpArea MpiplProcDumpArea; +typedef struct MpiplPreservedState MpiplPreservedState; +typedef struct MpiplPreservedCPUState MpiplPreservedCPUState; + /* Following offsets are copied from skiboot source code */ /* Use 768 bytes for SPIRAH */ #define SPIRAH_OFF 0x00010000 @@ -46,6 +52,8 @@ typedef struct MpiplPreservedState MpiplPreservedState; #define __packed __attribute__((packed)) +#define NUM_REGS_PER_CPU 34 /*(32 GPRs, NIP, MSR)*/ + /* * Memory Dump Source Table (MDST) * @@ -92,6 +100,55 @@ static_assert(MDST_MAX_ENTRIES == MDDT_MAX_ENTRIES, static_assert(MDRT_MAX_ENTRIES >= MDST_MAX_ENTRIES, "MDRT should support atleast having number of entries as in MDST"); +/* + * Processor Dump Area + * + * This contains the information needed for having processor + * state captured during a platform dump. + * + * As mentioned in HDAT, following the P9 specific format + */ +struct MpiplProcDumpArea { + uint32_t thread_size; /* Size of each thread register entry */ +#define PROC_DUMP_AREA_VERSION_P9 0x1 /* P9 format */ + uint8_t version; + uint8_t reserved[11]; + uint64_t alloc_addr; /* Destination memory to place register data */ + uint32_t reserved2; + uint32_t alloc_size; /* Allocated size */ + uint64_t dest_addr; /* Destination address */ + uint32_t reserved3; + uint32_t act_size; /* Actual data size */ +} __packed; + +/* + * "Architected Register Data" in the HDAT spec + * + * Acts as a header to the register entries for a particular thread + */ +struct MpiplRegDataHdr { + uint32_t pir; /* PIR of thread */ + uint8_t core_state; /* Stop state of the overall core */ + uint8_t reserved[3]; + uint32_t off_regentries; /* Offset to Register Entries Array */ + uint32_t num_regentries; /* Number of Register Entries in Array */ + uint32_t alloc_size; /* Allocated size for each Register Entry */ + uint32_t act_size; /* Actual size for each Register Entry */ +} __packed; + +struct MpiplRegEntry { + uint32_t reg_type; + uint32_t reg_num; + uint64_t reg_val; +} __packed; + +struct MpiplPreservedCPUState { + MpiplRegDataHdr hdr; + + /* Length of 'reg_entries' is hdr.num_regentries */ + MpiplRegEntry reg_entries[NUM_REGS_PER_CPU]; +}; + /* Preserved state to be saved in PnvMachineState */ struct MpiplPreservedState { /* skiboot_base will be valid only after OPAL sends relocated base to SBE */ @@ -100,6 +157,11 @@ struct MpiplPreservedState { MdrtTableEntry *mdrt_table; uint32_t num_mdrt_entries; + + MpiplProcDumpArea proc_area; + + MpiplPreservedCPUState *cpu_states; + uint32_t num_cpu_states; }; #endif -- 2.52.0