From: Anton Johansson via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [PATCH 1/7] target/alpha: Introduce alpha_phys_addr_space_bits()
Date: Tue, 09 Dec 2025 14:56:02 +0100 [thread overview]
Message-ID: <20251209-phys_addr-v1-1-c387f3e72d77@rev.ng> (raw)
In-Reply-To: <20251209-phys_addr-v1-0-c387f3e72d77@rev.ng>
In preparation for dropping TARGET_PHYS_ADDR_SPACE_BITS, add a
a runtime function to correctly represent the size of the physical
address space for EV4-6 based on the current CPU version.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
linux-user/alpha/target_proc.h | 2 +-
target/alpha/cpu.h | 1 +
target/alpha/helper.c | 18 ++++++++++++++++++
3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/linux-user/alpha/target_proc.h b/linux-user/alpha/target_proc.h
index da437ee0e5..bcdd1e343c 100644
--- a/linux-user/alpha/target_proc.h
+++ b/linux-user/alpha/target_proc.h
@@ -57,7 +57,7 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
"L1 Dcache\t\t: n/a\n"
"L2 cache\t\t: n/a\n"
"L3 cache\t\t: n/a\n",
- model, TARGET_PAGE_SIZE, TARGET_PHYS_ADDR_SPACE_BITS,
+ model, TARGET_PAGE_SIZE, alpha_phys_addr_space_bits(cpu_env),
max_cpus, num_cpus, cpu_mask);
return 0;
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 45944e46b5..9ee8d93b72 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -286,6 +286,7 @@ bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);
hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
#endif /* !CONFIG_USER_ONLY */
void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
+uint8_t alpha_phys_addr_space_bits(CPUAlphaState *env);
int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index a9af52a928..0f0cf73bf3 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -523,6 +523,24 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "\n");
}
+uint8_t alpha_phys_addr_space_bits(CPUAlphaState *env)
+{
+ switch (env->implver) {
+ case IMPLVER_2106x:
+ /* EV4 */
+ return 34;
+ case IMPLVER_21164:
+ /* EV5 */
+ return 40;
+ case IMPLVER_21264:
+ case IMPLVER_21364:
+ /* EV6 and EV7*/
+ return 44;
+ default:
+ g_assert_not_reached();
+ }
+}
+
/* This should only be called from translate, via gen_excp.
We expect that ENV->PC has already been updated. */
G_NORETURN void helper_excp(CPUAlphaState *env, int excp, int error)
--
2.51.0
next prev parent reply other threads:[~2025-12-09 13:54 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-09 13:56 [PATCH 0/7] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS Anton Johansson via
2025-12-09 13:56 ` Anton Johansson via [this message]
2025-12-11 15:09 ` [PATCH 1/7] target/alpha: Introduce alpha_phys_addr_space_bits() Richard Henderson
2025-12-09 13:56 ` [PATCH 2/7] target/hppa: Define PA[20|1X] physical address space size Anton Johansson via
2025-12-11 15:16 ` Richard Henderson
2025-12-09 13:56 ` [PATCH 3/7] target/i386: Drop physical address range checks Anton Johansson via
2025-12-09 13:56 ` [PATCH 4/7] target/loongarch: Introduce loongarch_palen_mask() Anton Johansson via
2025-12-09 13:56 ` [PATCH 5/7] hw/loongarch: Use loongarch_palen_mask() Anton Johansson via
2025-12-09 13:56 ` [PATCH 6/7] hw/riscv: Fix IOMMU PAS capability to 56 bits Anton Johansson via
2025-12-09 13:56 ` [PATCH 7/7] Drop TARGET_PHYS_ADDR_SPACE_BITS Anton Johansson via
2025-12-09 16:07 ` Brian Cain
2025-12-11 15:18 ` Richard Henderson
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