[PATCH 6/7] hw/riscv: Fix IOMMU PAS capability to 56 bits

[Anton Johansson via <qemu-devel@nongnu.org>]

Replaces the only remaining use of TARGET_PHYS_ADDR_SPACE_BITS for RISCV
with the fixed size of the riscv64 physical address space.

Better would be to somehow determine if a 32-bit or 64-bit cpu is
running and set accordingly, but I'm not sure how that would be done
from the device instance init function. This field is unused anyway.

Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 hw/riscv/riscv-iommu.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index f8656ec04b..573c536824 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -2448,9 +2448,15 @@ static void riscv_iommu_instance_init(Object *obj)
     /* Enable translation debug interface */
     s->cap = RISCV_IOMMU_CAP_DBG;
 
-    /* Report QEMU target physical address space limits */
-    s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,
-                       TARGET_PHYS_ADDR_SPACE_BITS);
+    /*
+     * Report QEMU target physical address space limits.
+     *
+     * Currently set to the riscv64 limit of 56 bits (44 bit PPN),
+     * riscv32 would use 34 bits (22 bit PPN).
+     *
+     * This field is currently unused.
+     */
+    s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS, 56);
 
     /* TODO: method to report supported PID bits */
     s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */

-- 
2.51.0