From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7431D1CDC6 for ; Tue, 9 Dec 2025 13:54:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vSyA2-0000Hj-Tn; Tue, 09 Dec 2025 08:53:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vSy9a-000094-1e for qemu-devel@nongnu.org; Tue, 09 Dec 2025 08:53:28 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vSy9X-0002cf-51 for qemu-devel@nongnu.org; Tue, 09 Dec 2025 08:53:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=9F56ezpJQPKpkmce3eQhs7nQ1rueuwE3dX3pcpOdYMo=; b=nAdR7gSyUikkmYx fe5I2PerWs7FxRDttmEhQBPA5w5I3FBkRMNuaXGpPc8K3+r5VUzSwNICTo5/UvkNYxNdlNpWAV0NQ RQlpXdrOyIhAvWlAFDDqgjHmit66iGvHdnR5FyexOS/6EBVyyxzz+IT+Qu8b0SC9GLv+0zED1lh2i BU=; Date: Tue, 09 Dec 2025 14:56:07 +0100 Subject: [PATCH 6/7] hw/riscv: Fix IOMMU PAS capability to 56 bits MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251209-phys_addr-v1-6-c387f3e72d77@rev.ng> References: <20251209-phys_addr-v1-0-c387f3e72d77@rev.ng> In-Reply-To: <20251209-phys_addr-v1-0-c387f3e72d77@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replaces the only remaining use of TARGET_PHYS_ADDR_SPACE_BITS for RISCV with the fixed size of the riscv64 physical address space. Better would be to somehow determine if a 32-bit or 64-bit cpu is running and set accordingly, but I'm not sure how that would be done from the device instance init function. This field is unused anyway. Signed-off-by: Anton Johansson --- hw/riscv/riscv-iommu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index f8656ec04b..573c536824 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2448,9 +2448,15 @@ static void riscv_iommu_instance_init(Object *obj) /* Enable translation debug interface */ s->cap = RISCV_IOMMU_CAP_DBG; - /* Report QEMU target physical address space limits */ - s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS, - TARGET_PHYS_ADDR_SPACE_BITS); + /* + * Report QEMU target physical address space limits. + * + * Currently set to the riscv64 limit of 56 bits (44 bit PPN), + * riscv32 would use 34 bits (22 bit PPN). + * + * This field is currently unused. + */ + s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS, 56); /* TODO: method to report supported PID bits */ s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */ -- 2.51.0