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Wed, 10 Dec 2025 15:29:34 -0800 (PST) Date: Wed, 10 Dec 2025 23:29:11 +0000 Mime-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAEcCOmkC/13M0QrCIBTG8VcZ5zpDXTrsqveILkzP3IHKoSHF2 LvnBhHr8vvg/5sgYyLMcGwmSFgoU3zU0e4acIN9BGTk6wbJpRKCK2bziOhZDiNFJvzBeNQOrdZ QkzFhT6+VO1/qHig/Y3qvehHL+4X0FiqCcXblUnPTdkL39hRiDDfcu3iHRSryV0tu/mpZa9NpV L3qDHdyU8/z/AHyaNmg5wAAAA== X-Change-Id: 20251105-aspeed-sgpio-1d49de6cea66 X-Mailer: b4 0.14.2 Message-ID: <20251210-aspeed-sgpio-v3-0-eb8b0cf3dd51@google.com> Subject: [PATCH v3 0/6] hw/gpio/aspeed_sgpio: Add Aspeed Serial GPIO (SGPIO) controller model From: Yubin Zou To: qemu-devel@nongnu.org Cc: "=?utf-8?q?C=C3=A9dric_Le_Goater?=" , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Kane-Chen-AS , Nabih Estefan , qemu-arm@nongnu.org, Yubin Zou Content-Type: text/plain; charset="utf-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::649; envelope-from=3XgI6aQYKCpsTP6DIUBJJBG9.7JHL9HP-89Q9GIJIBIP.JMB@flex--yubinz.bounces.google.com; helo=mail-pl1-x649.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series introduces a model for the Aspeed Serial GPIO (SGPIO) controller, commonly found on Aspeed SoCs such as the AST2700. The SGPIO peripheral provides a large number of GPIO pins that can be controlled and monitored serially. Improvement to QEMU: These patches enhance QEMU's hardware emulation capabilities for platforms using Aspeed SoCs, particularly for BMC simulations. By modeling the SGPIO controller, QEMU can more accurately represent the hardware, allowing for better development and testing of firmware and software that relies on these GPIOs for various functions like sensor monitoring, presence detect, and system control signals. Impact (Before/After): Before: QEMU lacked a model for the Aspeed SGPIO controller. Any guest software attempting to interact with the SGPIO register space would find no device. Firmware features depending on SGPIO pin states or interrupts could not be tested in QEMU. After: QEMU emulates the Aspeed SGPIO controller on supported machines (e.g., ast2700-evb). - Guest firmware can configure SGPIO pins, set output values, and read input values through the memory-mapped registers. - External entities (like test scripts or other QEMU components) can interact with the pins via QOM properties (e.g., to simulate external signal changes). Path example: /machine/soc/sgpio[0]/sgpio0 - The model generates interrupts based on input pin transitions, according to the configured mode (level/edge), enabling testing of interrupt handlers. Signed-off-by: Yubin Zou --- Changes in v3: - Fix commit message typo and address several review feedback in commit 2/6. - Switch to use g_autofree and drop g_free. - Use "%03d" instead of "%d". - Link to v2: https://lore.kernel.org/qemu-devel/20251209-aspeed-sgpio-v2-0-976e5f5790c2@google.com Changes in v2: Split the v1 into smaller commits and reorder it for better review: - Link to v1: https://lore.kernel.org/qemu-devel/20251106-aspeed-sgpio-v1-0-b026093716fa@google.com --- Yubin Zou (6): hw/gpio/aspeed_sgpio: Add basic device model for Aspeed SGPIO hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins hw/gpio/aspeed_sgpio: Implement SGPIO interrupt handling hw/arm/aspeed_soc: Update Aspeed SoC to support two SGPIO controllers hw/arm/aspeed_ast27x0: Wire SGPIO controller to AST2700 SoC test/qtest: Add Unit test for Aspeed SGPIO include/hw/arm/aspeed_soc.h | 8 +- include/hw/gpio/aspeed_sgpio.h | 68 ++++++++ hw/arm/aspeed_ast10x0.c | 6 +- hw/arm/aspeed_ast27x0.c | 26 +++ hw/gpio/aspeed_sgpio.c | 348 +++++++++++++++++++++++++++++++++++++++ tests/qtest/ast2700-sgpio-test.c | 152 +++++++++++++++++ hw/gpio/meson.build | 1 + tests/qtest/meson.build | 1 + 8 files changed, 605 insertions(+), 5 deletions(-) --- base-commit: 917ac07f9aef579b9538a81d45f45850aba42906 change-id: 20251105-aspeed-sgpio-1d49de6cea66 Best regards, -- Yubin Zou