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envelope-from=jrossi@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jared Rossi Define selected s390x PCI instructions and extend IPLB to allow PCI devices. Signed-off-by: Jared Rossi --- pc-bios/s390-ccw/pci.h | 88 ++++++++++ pc-bios/s390-ccw/pci.c | 331 ++++++++++++++++++++++++++++++++++++++ pc-bios/s390-ccw/Makefile | 2 +- 3 files changed, 420 insertions(+), 1 deletion(-) create mode 100644 pc-bios/s390-ccw/pci.h create mode 100644 pc-bios/s390-ccw/pci.c diff --git a/pc-bios/s390-ccw/pci.h b/pc-bios/s390-ccw/pci.h new file mode 100644 index 0000000000..847cf3f194 --- /dev/null +++ b/pc-bios/s390-ccw/pci.h @@ -0,0 +1,88 @@ +/* + * s390x PCI definitions + * + * Copyright 2025 IBM Corp. + * Author(s): Jared Rossi + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef PCI_H +#define PCI_H + +#include +#include +#include "clp.h" + +#define ZPCI_CREATE_REQ(handle, space, len) \ + ((uint64_t) handle << 32 | space << 16 | len) + +union register_pair { + unsigned __int128 pair; + struct { + unsigned long even; + unsigned long odd; + }; +}; + +#define PCIFIB_FC_ENABLED 0x80 +#define PCIFIB_FC_ERROR 0x40 +#define PCIFIB_FC_BLOCKED 0x20 +#define PCIFIB_FC_DMAREG 0x10 + +#define PCIST_DISABLED 0x0 +#define PCIST_ENABLED 0x1 + +#define PCI_CFGBAR 0xF /* Base Address Register for config space */ +#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ + +struct PciFib { + uint32_t reserved0[2]; + uint8_t fcflags; + uint8_t reserved1[3]; + uint32_t reserved2; + uint64_t pba; + uint64_t pal; + uint64_t iota; + uint16_t isc:4; + uint16_t noi:12; + uint8_t reserved3:2; + uint8_t aibvo:6; + uint8_t s:1; + uint8_t reserved4:1; + uint8_t aisbo:6; + uint32_t reserved5; + uint64_t aibv; + uint64_t aisb; + uint64_t fmba; + uint32_t reserved6[2]; +}; +typedef struct PciFib PciFib; + +struct PciDevice { + uint16_t device_id; + uint16_t vendor_id; + uint32_t fid; + uint32_t fhandle; + uint8_t status; + PciFib fib; +}; +typedef struct PciDevice PciDevice; + +int pci_write_flex(uint32_t fhandle, uint64_t offset, uint8_t pcias, void *data, int len); +int pci_write_byte(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint8_t data); +int pci_bswap16_write(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint16_t data); +int pci_bswap32_write(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint32_t data); +int pci_bswap64_write(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint64_t data); + +int pci_read_flex(uint32_t fhandle, uint64_t offset, uint8_t pcias, void *buf, int len); +int pci_read_bswap64(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint64_t *buf); +int pci_read_bswap32(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint32_t *buf); +int pci_read_bswap16(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint16_t *buf); +int pci_read_byte(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint8_t *buf); + +int pci_dev_enable(PciDevice *pcidev); +int get_fib(PciFib *fib, uint32_t fhandle); +int set_fib(PciFib *fib, uint32_t fhandle, uint8_t dma_as, uint8_t opcontrol); + +#endif diff --git a/pc-bios/s390-ccw/pci.c b/pc-bios/s390-ccw/pci.c new file mode 100644 index 0000000000..c149789386 --- /dev/null +++ b/pc-bios/s390-ccw/pci.c @@ -0,0 +1,331 @@ +/* + * s390x PCI funcionality + * + * Copyright 2025 IBM Corp. + * Author(s): Jared Rossi + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "clp.h" +#include "pci.h" +#include "bswap.h" +#include +#include + +/* PCI load */ +static inline int pcilg(uint64_t *data, uint64_t req, uint64_t offset, uint8_t *status) +{ + union register_pair req_off = {.even = req, .odd = offset}; + int cc = -1; + uint64_t __data; + + asm volatile ( + " .insn rre,0xb9d20000,%[data],%[req_off]\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "+d" (cc), [data] "=d" (__data), + [req_off] "+d" (req_off.pair) :: "cc"); + *status = req_off.even >> 24 & 0xff; + *data = __data; + return cc; +} + +/* PCI store */ +int pcistg(uint64_t data, uint64_t req, uint64_t offset, uint8_t *status) +{ + union register_pair req_off = {.even = req, .odd = offset}; + int cc = -1; + + asm volatile ( + " .insn rre,0xb9d00000,%[data],%[req_off]\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "+d" (cc), [req_off] "+d" (req_off.pair) + : [data] "d" (data) + : "cc"); + *status = req_off.even >> 24 & 0xff; + return cc; +} + +/* store PCI function controls */ +int stpcifc(uint64_t req, PciFib *fib, uint8_t *status) +{ + uint8_t cc; + + asm volatile ( + " .insn rxy,0xe300000000d4,%[req],%[fib]\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib) + : : "cc"); + *status = req >> 24 & 0xff; + return cc; +} + +/* modify PCI function controls */ +int mpcifc(uint64_t req, PciFib *fib, uint8_t *status) +{ + uint8_t cc; + + asm volatile ( + " .insn rxy,0xe300000000d0,%[req],%[fib]\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib) + : : "cc"); + *status = req >> 24 & 0xff; + return cc; +} + +static int pci_write(uint32_t fhandle, uint64_t offset, uint8_t pcias, + uint64_t data, uint8_t len) +{ + + uint64_t req = ZPCI_CREATE_REQ(fhandle, pcias, len); + uint8_t status; + int rc; + + /* writes must be non-zero powers of 2 with a maximum of 8 bytes per read */ + switch (len) { + case 1: + case 2: + case 4: + case 8: + rc = pcistg(data, req, offset, &status); + break; + default: + rc = -1; + } + + /* Error condition detected */ + if (rc == 1) { + printf("PCI store failed with status condition %d\n", status); + return -1; + } + + return rc ? -1 : 0; +} + +/* Write an arbitrary length of data without byte swapping */ +int pci_write_flex(uint32_t fh, uint64_t offset, uint8_t pcias, void *data, int len) +{ + uint8_t writelen, tmp; + int rc; + int remaining = len; + + /* write bytes in powers of 2, up to a maximum of 8 bytes per read */ + while (remaining) { + if (remaining > 7) { + writelen = 8; + } else { + writelen = 1; + while (true) { + tmp = writelen * 2; + if (tmp > remaining) { + break; + } + + writelen = tmp; + } + } + + /* Access next data based on write size */ + switch (writelen) { + case 1: + rc = pci_write(fh, offset, pcias, ((uint8_t *)data)[0], 1); + break; + case 2: + rc = pci_write(fh, offset, pcias, ((uint16_t *)data)[0], 2); + break; + case 4: + rc = pci_write(fh, offset, pcias, ((uint32_t *)data)[0], 4); + break; + case 8: + rc = pci_write(fh, offset, pcias, ((uint64_t *)data)[0], 8); + break; + default: + rc = -1; + } + + if (rc) { + return -1; + } + + remaining -= writelen; + data += writelen; + offset += writelen; + } + + return 0; +} + +int pci_write_byte(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint8_t data) +{ + return pci_write(fhandle, offset, pcias, (uint64_t)data, 1); +} + +/* Wrappers to byte swap common data sizes then write */ +int pci_bswap16_write(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint16_t data) +{ + uint64_t le_data = bswap16(data); + return pci_write(fhandle, offset, pcias, le_data, 2); +} + +int pci_bswap32_write(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint32_t data) +{ + uint64_t le_data = bswap32(data); + return pci_write(fhandle, offset, pcias, le_data, 4); +} + +int pci_bswap64_write(uint32_t fhandle, uint64_t offset, uint8_t pcias, uint64_t data) +{ + uint64_t le_data = bswap64(data); + return pci_write(fhandle, offset, pcias, le_data, 8); +} + +static int pci_read(uint32_t fh, uint64_t offset, uint8_t pcias, void *buf, uint8_t len) +{ + uint64_t req, data; + uint8_t status; + int rc; + + req = ZPCI_CREATE_REQ(fh, pcias, len); + rc = pcilg(&data, req, offset, &status); + + /* Error condition detected */ + if (rc == 1) { + printf("PCI load failed with status condition %d\n", status); + return -1; + } + + switch (len) { + case 1: + *(uint8_t *)buf = data; + break; + case 2: + *(uint16_t *)buf = data; + break; + case 4: + *(uint32_t *)buf = data; + break; + case 8: + *(uint64_t *)buf = data; + break; + default: + return -1; + } + + return rc ? -1 : 0; +} + +/* Read to an arbitrary length buffer without byte swapping */ +int pci_read_flex(uint32_t fh, uint64_t offset, uint8_t pcias, void *buf, int len) +{ + uint8_t readlen, tmp; + int rc; + int remaining = len; + + /* Read bytes in powers of 2, up to a maximum of 8 bytes per read */ + while (remaining) { + if (remaining > 7) { + readlen = 8; + } else { + readlen = 1; + while (true) { + tmp = readlen * 2; + if (tmp > remaining) { + break; + } + + readlen = tmp; + } + } + + rc = pci_read(fh, offset, pcias, buf, readlen); + if (rc) { + return -1; + } + + remaining -= readlen; + buf += readlen; + offset += readlen; + } + + return 0; +} + +int pci_read_byte(uint32_t fh, uint64_t offset, uint8_t pcias, uint8_t *buf) +{ + return pci_read(fh, offset, pcias, buf, 1); +} + +/* Wrappers to read common data sizes then byte swap */ +int pci_read_bswap16(uint32_t fh, uint64_t offset, uint8_t pcias, uint16_t *buf) +{ + int rc = pci_read(fh, offset, pcias, buf, 2); + *buf = bswap16(*buf); + return rc; +} + +int pci_read_bswap32(uint32_t fh, uint64_t offset, uint8_t pcias, uint32_t *buf) +{ + int rc = pci_read(fh, offset, pcias, buf, 4); + *buf = bswap32(*buf); + return rc; +} + +int pci_read_bswap64(uint32_t fh, uint64_t offset, uint8_t pcias, uint64_t *buf) +{ + int rc = pci_read(fh, offset, pcias, buf, 8); + *buf = bswap64(*buf); + return rc; +} + +int pci_dev_enable(PciDevice *pcidev) +{ + int rc; + + rc = enable_pci_function(&pcidev->fhandle); + if (rc) { + return rc; + } + + pcidev->status = PCIST_ENABLED; + + return get_fib(&pcidev->fib, pcidev->fhandle); +} + +int get_fib(PciFib *fib, uint32_t fhandle) +{ + uint64_t req = ZPCI_CREATE_REQ(fhandle, 0, 0); + uint8_t status; + int rc; + + rc = stpcifc(req, fib, &status); + + if (rc == 1) { + return status; + } else if (rc) { + return rc; + } + + return 0; +} + +int set_fib(PciFib *fib, uint32_t fhandle, uint8_t dma_as, uint8_t opcontrol) +{ + uint64_t req = ZPCI_CREATE_REQ(fhandle, dma_as, opcontrol); + uint8_t status; + int rc; + + rc = mpcifc(req, fib, &status); + + if (rc == 1) { + return status; + } else if (rc) { + return rc; + } + + return 0; +} diff --git a/pc-bios/s390-ccw/Makefile b/pc-bios/s390-ccw/Makefile index 9c29548f84..a62fc9d766 100644 --- a/pc-bios/s390-ccw/Makefile +++ b/pc-bios/s390-ccw/Makefile @@ -35,7 +35,7 @@ QEMU_DGFLAGS = -MMD -MP -MT $@ -MF $(@D)/$(*F).d OBJECTS = start.o main.o bootmap.o jump2ipl.o sclp.o menu.o netmain.o \ virtio.o virtio-net.o virtio-scsi.o virtio-blkdev.o cio.o dasd-ipl.o \ - virtio-ccw.o clp.o + virtio-ccw.o clp.o pci.o SLOF_DIR := $(SRC_PATH)/../../roms/SLOF -- 2.49.0