From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89F2CD3E793 for ; Thu, 11 Dec 2025 05:44:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vTZT9-0000hp-4O; Thu, 11 Dec 2025 00:44:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vTZT3-0000ej-Lz for qemu-devel@nongnu.org; Thu, 11 Dec 2025 00:43:57 -0500 Received: from mgamail.intel.com ([192.198.163.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vTZT2-0001OC-3z for qemu-devel@nongnu.org; Thu, 11 Dec 2025 00:43:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765431836; x=1796967836; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FovsNeUNQb3Mbfo6UFh8WpHvsMB68L7Ws+8KaJE9y0g=; b=UcXA2q2DnkUyi8QH6Ak/HFJGCtmxdT42VKcmJb0wfqLrsHvxpkTX1qaH 6o80sZcW5P0jTOJt1TPMZWobr/sX6owSSwhX5Ak9+udRb4OoKpzftLQWk O9xoR0rL4QfRBK8U/SLUc72zL+8nKIcAw+YnHvBf8vTwU9VTatfOEXSyz 2i+eKQ3i6kyl+Q3dZUtbmonrAmzAUlHiau4fVIQkYJ+Jyi+Az/+odAmoP TVoOXFUAR/2dEQkKbxDM1jOfKH2vMKlpwgvMC7ACb8BVLCmy1/yITZHv3 EBaK5dWXUvfqvEHar1mWGyLcYMn8IznmUP21urzgTNwGWzziaHZn2yyuV g==; X-CSE-ConnectionGUID: WuFEFt9nQ5yCg6o1lcIkyg== X-CSE-MsgGUID: 3jAF0gsDTumRWijg5a4OUw== X-IronPort-AV: E=McAfee;i="6800,10657,11638"; a="66409887" X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="66409887" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2025 21:43:55 -0800 X-CSE-ConnectionGUID: JHbUU9LCTeSpZFIdC6bKkw== X-CSE-MsgGUID: WwYbV4ehQbOgFCvOn3sbzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="227366081" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa002.jf.intel.com with ESMTP; 10 Dec 2025 21:43:52 -0800 From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , Xin Li , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Xiaoyao Li , Chenyi Qiang , Farrah Chen , Zhao Liu Subject: [PATCH v5 09/22] i386/cpu: Fix supervisor xstate initialization Date: Thu, 11 Dec 2025 14:07:48 +0800 Message-Id: <20251211060801.3600039-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211060801.3600039-1-zhao1.liu@intel.com> References: <20251211060801.3600039-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=192.198.163.19; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Chao Gao Arch lbr is a supervisor xstate, but its area is not covered in x86_cpu_init_xsave(). Fix it by checking supported xss bitmap. In addition, drop the (uint64_t) type casts for supported_xcr0 since x86_cpu_get_supported_feature_word() returns uint64_t so that the cast is not needed. Then ensure line length is within 90 characters. Tested-by: Farrah Chen Reviewed-by: Xiaoyao Li Signed-off-by: Chao Gao Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- Changes Since v3: - Fix shift for CXRO high 32 bits. --- target/i386/cpu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 62769db3ebb7..859cb889a37c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9711,20 +9711,23 @@ static void x86_cpu_post_initfn(Object *obj) static void x86_cpu_init_xsave(void) { static bool first = true; - uint64_t supported_xcr0; + uint64_t supported_xcr0, supported_xss; int i; if (first) { first = false; supported_xcr0 = - ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | + x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32 | x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); + supported_xss = + x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XSS_HI) << 32 | + x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XSS_LO); for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { ExtSaveArea *esa = &x86_ext_save_areas[i]; - if (!(supported_xcr0 & (1 << i))) { + if (!((supported_xcr0 | supported_xss) & (1 << i))) { esa->size = 0; } } -- 2.34.1