From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 566FBD3E793 for ; Thu, 11 Dec 2025 05:44:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vTZTD-0000n2-SO; Thu, 11 Dec 2025 00:44:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vTZTB-0000j9-Vt for qemu-devel@nongnu.org; Thu, 11 Dec 2025 00:44:06 -0500 Received: from mgamail.intel.com ([192.198.163.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vTZTA-0001bl-8w for qemu-devel@nongnu.org; Thu, 11 Dec 2025 00:44:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765431844; x=1796967844; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DZ3sfvrb+qc8GsNdFeIp7NVIUjHrM1Kf/7Vu9/XqA3o=; b=NoU0M0NXQt112mno62ojSJwj6qLi+/RQGhzZsZcW1d1I6GK7r12NHzIM fvzWAO5XkiZRwseP8OGX5QmTENxcFdPX1VaQXrkaUhmDm+otsZ0EITSW4 XpJFIO4VM/uJhNlVSSZoKseYdALt6YWaYfCBvgxSNOlv8i+YTVv4ZC6LH Cpx8DUToEuYqb1BqaBjRG6U/rxfJWKhpo0R31zuVEqK/sBqWsdVnyijFV z1UuQNstWhB/8HpTf/v2ogoqkkjfYFQa+HclHw1KfZ1lmRySZH/Ud8BpY mpMdEkbeMuGdCZfT/qKI93KqtZtbNHSnZ9ByiUQ4GXTzG9AtzlcuvpeBK Q==; X-CSE-ConnectionGUID: vPtfC1O8R+q1WSXW/6APMQ== X-CSE-MsgGUID: LTO+qNK1TuifJs93dH7Oww== X-IronPort-AV: E=McAfee;i="6800,10657,11638"; a="66409903" X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="66409903" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2025 21:44:03 -0800 X-CSE-ConnectionGUID: QoC2Q5C0S7m/fEn5mdfr1g== X-CSE-MsgGUID: FcG2oCBHSzGtD+rfLRUnwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="227366094" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa002.jf.intel.com with ESMTP; 10 Dec 2025 21:43:55 -0800 From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , Xin Li , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Xiaoyao Li , Chenyi Qiang , Farrah Chen , Zhao Liu Subject: [PATCH v5 10/22] i386/cpu: Add missing migratable xsave features Date: Thu, 11 Dec 2025 14:07:49 +0800 Message-Id: <20251211060801.3600039-11-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211060801.3600039-1-zhao1.liu@intel.com> References: <20251211060801.3600039-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=192.198.163.19; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Xtile-cfg & xtile-data are both user xstates. Their xstates are cached in X86CPUState, and there's a related vmsd "vmstate_amx_xtile", so that it's safe to mark them as migratable. Arch lbr xstate is a supervisor xstate, and it is save & load by saving & loading related arch lbr MSRs, which are cached in X86CPUState, and there's a related vmsd "vmstate_arch_lbr". So it should be migratable. PT is still unmigratable since KVM disabled it and there's no vmsd and no other emulation/simulation support. Note, though the migratable_flags get fixed, x86_cpu_enable_xsave_components() still overrides supported xstates bitmaps regardless the masking of migratable_flags. This is another issue, and would be fixed in follow-up refactoring. Tested-by: Farrah Chen Signed-off-by: Zhao Liu --- Changes Since v3: - Mark XSTATE_ARCH_LBR_MASK as migratable in FEAT_XSAVE_XSS_LO. - Add TODO comment. --- target/i386/cpu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 859cb889a37c..d2a89c03caec 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1484,6 +1484,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .ecx = 1, .reg = R_ECX, }, + .migratable_flags = XSTATE_ARCH_LBR_MASK, }, [FEAT_XSAVE_XSS_HI] = { .type = CPUID_FEATURE_WORD, @@ -1522,7 +1523,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | - XSTATE_PKRU_MASK, + XSTATE_PKRU_MASK | XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK, }, [FEAT_XSAVE_XCR0_HI] = { .type = CPUID_FEATURE_WORD, @@ -2154,8 +2155,13 @@ static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) for (i = 0; i < 64; i++) { uint64_t f = 1ULL << i; - /* If the feature name is known, it is implicitly considered migratable, - * unless it is explicitly set in unmigratable_flags */ + /* + * If the feature name is known, it is implicitly considered migratable, + * unless it is explicitly set in unmigratable_flags. + * + * TODO: Make the behavior of x86_cpu_enable_xsave_components() align + * with migratable_flags masking. + */ if ((wi->migratable_flags & f) || (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { r |= f; -- 2.34.1