From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0003D3E782 for ; Thu, 11 Dec 2025 05:44:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vTZSx-0000dB-QL; Thu, 11 Dec 2025 00:43:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vTZSp-0000bo-Oj for qemu-devel@nongnu.org; Thu, 11 Dec 2025 00:43:45 -0500 Received: from mgamail.intel.com ([192.198.163.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vTZSo-0001OC-84 for qemu-devel@nongnu.org; Thu, 11 Dec 2025 00:43:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765431822; x=1796967822; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=c/VS1/2chdkAwU46yWRjXngVNYQ5YwGggg1BKVSm57Q=; b=Cxj4Ay6VeTDGMe8SmCJm857q/MgZ1Agmq28TYfvpVWW7/q9B1pWyetD0 GKft6KcDlQ8R8/aiTaNxQ7LZDNE44jjwKOxeSWYCWojLRkgvpKgi182ZS ptMilJRJN4zbE7JP+dzoHAHsaGeb9D3+kc0ULfQ2ufZaISY7O1hRuwty4 vEudsQN7queMNDa5kE49WEAsrIe9KOrwcV1S+WRktxBuPbjUUyLndzZDb C/Afc6n8de4kBqwO3/NNCiN1WDKRb6f5q2lIS/rzlzvYHcGiziz1F2rNA h/VTgramVtj/w48RMCulxWarDOMa5vRZlj8eB7yaRK0FoYJpK7/NWpr6M g==; X-CSE-ConnectionGUID: QEip/jjvTCaI7vZNBT8+Kg== X-CSE-MsgGUID: 6trea5+bQSiKGEdelfmcDg== X-IronPort-AV: E=McAfee;i="6800,10657,11638"; a="66409851" X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="66409851" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2025 21:43:41 -0800 X-CSE-ConnectionGUID: LL4fL7cESH+fVaf4NISmLQ== X-CSE-MsgGUID: 5+6778LAS42EFOp529m5Bw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="227366032" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa002.jf.intel.com with ESMTP; 10 Dec 2025 21:43:37 -0800 From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , Xin Li , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Xiaoyao Li , Chenyi Qiang , Farrah Chen , Zhao Liu Subject: [PATCH v5 05/22] i386/cpu: Add avx10 dependency for Opmask/ZMM_Hi256/Hi16_ZMM Date: Thu, 11 Dec 2025 14:07:44 +0800 Message-Id: <20251211060801.3600039-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211060801.3600039-1-zhao1.liu@intel.com> References: <20251211060801.3600039-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=192.198.163.19; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org With feature array in ExtSaveArea, add avx10 as the second dependency for Opmask/ZMM_Hi256/Hi16_ZMM xsave components, and drop the special check in cpuid_has_xsave_feature(). Tested-by: Farrah Chen Reviewed-by: Xiaoyao Li Signed-off-by: Zhao Liu --- target/i386/cpu.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e495e6d9b21c..70a282668f72 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2054,18 +2054,21 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { .size = sizeof(XSaveOpmask), .features = { { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F }, + { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, }, }, [XSTATE_ZMM_Hi256_BIT] = { .size = sizeof(XSaveZMM_Hi256), .features = { { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F }, + { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, }, }, [XSTATE_Hi16_ZMM_BIT] = { .size = sizeof(XSaveHi16_ZMM), .features = { { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F }, + { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, }, }, [XSTATE_PKRU_BIT] = { @@ -8648,12 +8651,6 @@ static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) } } - if (esa->features[0].index == FEAT_7_0_EBX && - esa->features[0].mask == CPUID_7_0_EBX_AVX512F && - (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { - return true; - } - return false; } -- 2.34.1