From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B4E9D3E793 for ; Thu, 11 Dec 2025 05:45:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vTZT6-0000fE-NS; Thu, 11 Dec 2025 00:44:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vTZT0-0000e0-P4 for qemu-devel@nongnu.org; Thu, 11 Dec 2025 00:43:55 -0500 Received: from mgamail.intel.com ([192.198.163.19]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vTZSz-0001OC-51 for qemu-devel@nongnu.org; Thu, 11 Dec 2025 00:43:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765431833; x=1796967833; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fJBFcQVoKmgeoUmwsBmvZdBtcnTJvhtd89N47vMSmQc=; b=jaC5OmT7DffCUReXu9G2D1kscOc9wBuvnjct0B57dvTpyJm5lYrds89Q 7WJherJSzMpwElt6lFb3JFMsfUTX/1oBbq8x76SduQs6gcDUFGaHRHfeI wyR57v7KU64CZp7/q9QIyms8Nqzd8vfoOpndkwYaioz727e9KUUYFc/IU sURDol72bd1xGr8mLJd3BRkV5ALJQhBBaT2kqV8N1ZSkFpVk9PxmJ3y4h MBk+83+TgS/FOU2/nDX+SrAa8xlCegrRjfG8W1F0yRUbJynLmzXlvNyJY mwMftL2rI2pwVKQltL/y2fIQw59W9b1VfQxV9TZ4+Yu94X/oi5kvQ2BeB w==; X-CSE-ConnectionGUID: z5OqIvHmQJKNH4rP6h/C6A== X-CSE-MsgGUID: 60Pdw4cHS1GNUQd7+CihAQ== X-IronPort-AV: E=McAfee;i="6800,10657,11638"; a="66409877" X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="66409877" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2025 21:43:52 -0800 X-CSE-ConnectionGUID: BS+knNYIRRygEl7jo6PxpQ== X-CSE-MsgGUID: ZnWECnVlTcGvVPdkV8+UkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,265,1758610800"; d="scan'208";a="227366063" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa002.jf.intel.com with ESMTP; 10 Dec 2025 21:43:48 -0800 From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , Xin Li , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Xiaoyao Li , Chenyi Qiang , Farrah Chen , Zhao Liu Subject: [PATCH v5 08/22] i386/cpu: Drop pmu check in CPUID 0x1C encoding Date: Thu, 11 Dec 2025 14:07:47 +0800 Message-Id: <20251211060801.3600039-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211060801.3600039-1-zhao1.liu@intel.com> References: <20251211060801.3600039-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=192.198.163.19; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Since CPUID_7_0_EDX_ARCH_LBR will be masked off if pmu is disabled, there's no need to check CPUID_7_0_EDX_ARCH_LBR feature with pmu. Tested-by: Farrah Chen Reviewed-by: Zide Chen Reviewed-by: Xiaoyao Li Signed-off-by: Zhao Liu --- target/i386/cpu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 56b4c57969c1..62769db3ebb7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8273,11 +8273,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } break; } - case 0x1C: - if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { - x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); - *edx = 0; + case 0x1C: /* Last Branch Records Information Leaf */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { + break; } + x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); + *edx = 0; /* EDX is reserved. */ break; case 0x1D: { /* AMX TILE, for now hardcoded for Sapphire Rapids*/ -- 2.34.1