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Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH v2 0/9] i386/cpu: Support APX for KVM Date: Thu, 11 Dec 2025 15:09:33 +0800 Message-Id: <20251211070942.3612547-1-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This series adds APX (Advanced Performance Extensions) support in QEMU to enable APX in Guest based on KVM (RFC v1 [1]). This series is based on CET v5: https://lore.kernel.org/qemu-devel/20251211060801.3600039-1-zhao1.liu@intel.com/ And you can also find the code here: https://gitlab.com/zhao.liu/qemu/-/commits/i386-all-for-dmr-v2.1-12-10-2025 Compared with v1 [2], v2 adds: * HMP support ("print" & "info registers"). * gdbstub support. Thanks for your review! Overview ======== Intel Advanced Performance Extensions (Intel APX) expands the Intel 64 instruction set architecture with access to more registers (16 additional general-purpose registers (GPRs) R16–R31) and adds various new features that improve general-purpose performance. The extensions are designed to provide efficient performance gains across a variety of workloads without significantly increasing silicon area or power consumption of the core. APX spec link (rev.07) is: https://cdrdv2.intel.com/v1/dl/getContent/861610 At QEMU side, the enabling work mainly includes three parts: 1. save/restore/migrate the xstate of APX. * APX xstate is a user xstate, but it reuses MPX xstate area in un-compacted XSAVE buffer. * To address this, QEMU will reject both APX and MPX if their CPUID feature bits are set at the same (in Patch 1). 2. add related CPUIDs support in feature words. 3. debug support, including HMP & gdbstub. Change Log ========== Changes sicne v1: * Expend current GPR array (CPUX86State.regs) to 32 elements instead of a new array. * HMP support ("print" & "info registers"). * gdbstub support. [1]: KVM RFC: https://lore.kernel.org/kvm/20251110180131.28264-1-chang.seok.bae@intel.com/ [2]: QEMU APX v1: https://lore.kernel.org/qemu-devel/20251118065817.835017-1-zhao1.liu@intel.com/ Thanks and Best Regards, Zhao --- Zhao Liu (6): i386/machine: Use VMSTATE_UINTTL_SUB_ARRAY for vmstate of CPUX86State.regs i386/gdbstub: Add APX support for gdbstub i386/cpu-dump: Dump entended GPRs for APX supported guest i386/monitor: Support EGPRs in hmp_print i386/cpu: Support APX CPUIDs i386/cpu: Mark APX xstate as migratable Zide Chen (3): i386/cpu: Add APX EGPRs into xsave area i386/cpu: Cache EGPRs in CPUX86State i386/cpu: Add APX migration support configs/targets/x86_64-softmmu.mak | 2 +- gdb-xml/i386-64bit-apx.xml | 26 +++++++++++ include/migration/cpu.h | 4 ++ target/i386/cpu-dump.c | 30 +++++++++++-- target/i386/cpu.c | 68 ++++++++++++++++++++++++++++- target/i386/cpu.h | 48 +++++++++++++++++++-- target/i386/gdbstub.c | 69 +++++++++++++++++++++++++++++- target/i386/machine.c | 27 +++++++++++- target/i386/monitor.c | 16 +++++++ target/i386/xsave_helper.c | 16 +++++++ 10 files changed, 293 insertions(+), 13 deletions(-) create mode 100644 gdb-xml/i386-64bit-apx.xml -- 2.34.1