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Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH v2 3/9] i386/cpu: Cache EGPRs in CPUX86State Date: Thu, 11 Dec 2025 15:09:36 +0800 Message-Id: <20251211070942.3612547-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251211070942.3612547-1-zhao1.liu@intel.com> References: <20251211070942.3612547-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=198.175.65.16; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Zide Chen Expend general registers array "regs" of CPUX86State to cache entended GPRs. Tested-by: Xudong Hao Signed-off-by: Zide Chen Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- Changes since v1: * Extend "regs" array instead of a new array. --- target/i386/cpu.h | 7 +++++-- target/i386/xsave_helper.c | 16 ++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 932982bd5dd6..9bf5d0b41efe 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1664,12 +1664,15 @@ typedef struct { uint64_t mask; } MTRRVar; +#define CPU_NB_EREGS64 32 #define CPU_NB_REGS64 16 #define CPU_NB_REGS32 8 #ifdef TARGET_X86_64 +#define CPU_NB_EREGS CPU_NB_EREGS64 #define CPU_NB_REGS CPU_NB_REGS64 #else +#define CPU_NB_EREGS CPU_NB_REGS32 #define CPU_NB_REGS CPU_NB_REGS32 #endif @@ -1901,7 +1904,7 @@ typedef struct CPUCaches { typedef struct CPUArchState { /* standard registers */ - target_ulong regs[CPU_NB_REGS]; + target_ulong regs[CPU_NB_EREGS]; target_ulong eip; target_ulong eflags; /* eflags register. During CPU emulation, CC flags and DF are set to zero because they are @@ -1958,7 +1961,7 @@ typedef struct CPUArchState { float_status mmx_status; /* for 3DNow! float ops */ float_status sse_status; uint32_t mxcsr; - ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16); + ZMMReg xmm_regs[CPU_NB_EREGS] QEMU_ALIGNED(16); ZMMReg xmm_t0 QEMU_ALIGNED(16); MMXReg mmx_t0; diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index 996e9f3bfef5..bab22587320d 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -140,6 +140,14 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen) memcpy(tiledata, &env->xtiledata, sizeof(env->xtiledata)); } + + e = &x86_ext_save_areas[XSTATE_APX_BIT]; + if (e->size && e->offset && buflen) { + XSaveAPX *apx = buf + e->offset; + + memcpy(apx, &env->regs[CPU_NB_REGS], + sizeof(env->regs[CPU_NB_REGS]) * (CPU_NB_EREGS - CPU_NB_REGS)); + } #endif } @@ -275,5 +283,13 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen) memcpy(&env->xtiledata, tiledata, sizeof(env->xtiledata)); } + + e = &x86_ext_save_areas[XSTATE_APX_BIT]; + if (e->size && e->offset) { + const XSaveAPX *apx = buf + e->offset; + + memcpy(&env->regs[CPU_NB_REGS], apx, + sizeof(env->regs[CPU_NB_REGS]) * (CPU_NB_EREGS - CPU_NB_REGS)); + } #endif } -- 2.34.1