From: Zhao Liu <zhao1.liu@intel.com>
To: "Paolo Bonzini" <pbonzini@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Peter Xu" <peterx@redhat.com>, "Fabiano Rosas" <farosas@suse.de>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
"Chang S . Bae" <chang.seok.bae@intel.com>,
Zide Chen <zide.chen@intel.com>,
Xudong Hao <xudong.hao@intel.com>, Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH v2 5/9] i386/cpu-dump: Dump entended GPRs for APX supported guest
Date: Thu, 11 Dec 2025 15:09:38 +0800 [thread overview]
Message-ID: <20251211070942.3612547-6-zhao1.liu@intel.com> (raw)
In-Reply-To: <20251211070942.3612547-1-zhao1.liu@intel.com>
Dump EGPRs when guest supports APX.
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since v1:
* New patch.
---
target/i386/cpu-dump.c | 30 +++++++++++++++++++++++++++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c
index 67bf31e0caaf..b51076f87115 100644
--- a/target/i386/cpu-dump.c
+++ b/target/i386/cpu-dump.c
@@ -354,8 +354,7 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
"RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
"R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
- "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
- "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
+ "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n",
env->regs[R_EAX],
env->regs[R_EBX],
env->regs[R_ECX],
@@ -371,7 +370,32 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
env->regs[12],
env->regs[13],
env->regs[14],
- env->regs[15],
+ env->regs[15]);
+
+ if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APX) {
+ qemu_fprintf(f, "R16=%016" PRIx64 " R17=%016" PRIx64 " R18=%016" PRIx64 " R19=%016" PRIx64 "\n"
+ "R20=%016" PRIx64 " R21=%016" PRIx64 " R22=%016" PRIx64 " R23=%016" PRIx64 "\n"
+ "R24=%016" PRIx64 " R25=%016" PRIx64 " R26=%016" PRIx64 " R27=%016" PRIx64 "\n"
+ "R28=%016" PRIx64 " R29=%016" PRIx64 " R30=%016" PRIx64 " R31=%016" PRIx64 "\n",
+ env->regs[16],
+ env->regs[17],
+ env->regs[18],
+ env->regs[19],
+ env->regs[20],
+ env->regs[21],
+ env->regs[22],
+ env->regs[23],
+ env->regs[24],
+ env->regs[25],
+ env->regs[26],
+ env->regs[27],
+ env->regs[28],
+ env->regs[29],
+ env->regs[30],
+ env->regs[31]);
+ }
+
+ qemu_fprintf(f, "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
env->eip, eflags,
eflags & DF_MASK ? 'D' : '-',
eflags & CC_O ? 'O' : '-',
--
2.34.1
next prev parent reply other threads:[~2025-12-11 6:46 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-11 7:09 [PATCH v2 0/9] i386/cpu: Support APX for KVM Zhao Liu
2025-12-11 7:09 ` [PATCH v2 1/9] i386/cpu: Add APX EGPRs into xsave area Zhao Liu
2025-12-11 7:09 ` [PATCH v2 2/9] i386/machine: Use VMSTATE_UINTTL_SUB_ARRAY for vmstate of CPUX86State.regs Zhao Liu
2025-12-11 7:09 ` [PATCH v2 3/9] i386/cpu: Cache EGPRs in CPUX86State Zhao Liu
2025-12-11 7:09 ` [PATCH v2 4/9] i386/gdbstub: Add APX support for gdbstub Zhao Liu
2025-12-11 7:09 ` Zhao Liu [this message]
2025-12-11 7:09 ` [PATCH v2 6/9] i386/monitor: Support EGPRs in hmp_print Zhao Liu
2025-12-11 7:09 ` [PATCH v2 7/9] i386/cpu: Add APX migration support Zhao Liu
2025-12-11 7:09 ` [PATCH v2 8/9] i386/cpu: Support APX CPUIDs Zhao Liu
2025-12-11 7:09 ` [PATCH v2 9/9] i386/cpu: Mark APX xstate as migratable Zhao Liu
2025-12-11 8:08 ` [PATCH v2 0/9] i386/cpu: Support APX for KVM Paolo Bonzini
2025-12-11 9:16 ` Zhao Liu
2025-12-11 9:42 ` Paolo Bonzini
2025-12-11 11:42 ` Zhao Liu
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