From: frank.chang@sifive.com
To: qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs),
Frank Chang <frank.chang@sifive.com>
Subject: [PATCH v3 2/6] target/riscv: Add a helper to return the current effective priv mode
Date: Fri, 12 Dec 2025 00:38:21 +0800 [thread overview]
Message-ID: <20251211163826.3998266-3-frank.chang@sifive.com> (raw)
In-Reply-To: <20251211163826.3998266-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
This helper returns the current effective privilege mode.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 37 +++++++++++++++++++++++++++++++++++++
target/riscv/cpu_helper.c | 15 +++++----------
2 files changed, 42 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8899bf7667a..f59052fe7dc 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -799,6 +799,43 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
}
#endif
+/*
+ * Returns the current effective privilege mode.
+ *
+ * @env: CPURISCVState
+ * @priv: The returned effective privilege mode.
+ * @virt: The returned effective virtualization mode.
+ *
+ * Returns true if the effective privilege mode is modified.
+ */
+static inline QEMU_ALWAYS_INLINE
+bool riscv_cpu_eff_priv(CPURISCVState *env, int *priv, bool *virt)
+{
+ int mode = env->priv;
+ bool virt_enabled = false;
+ bool mode_modified = false;
+
+#ifndef CONFIG_USER_ONLY
+ if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
+ mode = get_field(env->mstatus, MSTATUS_MPP);
+ virt_enabled = get_field(env->mstatus, MSTATUS_MPV) && (mode != PRV_M);
+ mode_modified = true;
+ } else {
+ virt_enabled = env->virt_enabled;
+ }
+#endif
+
+ if (priv) {
+ *priv = mode;
+ }
+
+ if (virt) {
+ *virt = virt_enabled;
+ }
+
+ return mode_modified;
+}
+
static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg,
target_long priv_ver,
uint32_t misa_ext)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index dd6c861a90e..da6e2d8fe3a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -45,19 +45,14 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
#else
bool virt = env->virt_enabled;
int mode = env->priv;
+ bool mode_modified = false;
/* All priv -> mmu_idx mapping are here */
if (!ifetch) {
- uint64_t status = env->mstatus;
-
- if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) {
- mode = get_field(env->mstatus, MSTATUS_MPP);
- virt = get_field(env->mstatus, MSTATUS_MPV) &&
- (mode != PRV_M);
- if (virt) {
- status = env->vsstatus;
- }
- }
+ mode_modified = riscv_cpu_eff_priv(env, &mode, &virt);
+ uint64_t status = (mode_modified && virt) ? env->vsstatus :
+ env->mstatus;
+
if (mode == PRV_S && get_field(status, MSTATUS_SUM)) {
mode = MMUIdx_S_SUM;
}
--
2.43.0
next prev parent reply other threads:[~2025-12-11 16:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-11 16:38 [PATCH v3 0/6] Fix Zjpm implementation frank.chang
2025-12-11 16:38 ` [PATCH v3 1/6] target/riscv: fix address masking frank.chang
2025-12-11 16:38 ` frank.chang [this message]
2025-12-11 16:38 ` [PATCH v3 3/6] target/riscv: Fix pointer masking PMM field selection logic frank.chang
2025-12-11 16:38 ` [PATCH v3 4/6] target/riscv: Fix pointer masking for virtual-machine load/store insns frank.chang
2025-12-11 16:38 ` [PATCH v3 5/6] target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm() frank.chang
2025-12-11 16:38 ` [PATCH v3 6/6] target/riscv: Fix pointer masking translation mode check bug frank.chang
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