From: frank.chang@sifive.com
To: qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs),
Frank Chang <frank.chang@sifive.com>
Subject: [PATCH v3 3/6] target/riscv: Fix pointer masking PMM field selection logic
Date: Fri, 12 Dec 2025 00:38:22 +0800 [thread overview]
Message-ID: <20251211163826.3998266-4-frank.chang@sifive.com> (raw)
In-Reply-To: <20251211163826.3998266-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
mstatus.MPV only records the previous virtualization state, and does not
affect pointer masking according to the Zjpm specification.
This patch rewrites riscv_pm_get_pmm() to follow the architectural
definition of Smmpm, Smnpm, and Ssnpm.
The resulting PMM selection logic for each mode is summarized below:
* mstatus.MXR = 1: pointer masking disabled
* Smmpm + Smnpm + Ssnpm:
M-mode: mseccfg.PMM
S-mode: menvcfg.PMM
U-mode: senvcfg.PMM
VS-mode: henvcfg.PMM
VU-mode: senvcfg.PMM
* Smmpm + Smnpm (RVS implemented):
M-mode: mseccfg.PMM
S-mode: menvcfg.PMM
U/VS/VU: disabled (Ssnpm not present)
* Smmpm + Smnpm (RVS not implemented):
M-mode: mseccfg.PMM
U-mode: menvcfg.PMM
S/VS/VU: disabled (no S-mode)
* Smmpm only:
M-mode: mseccfg.PMM
Other existing modes: pointer masking disabled
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu_helper.c | 51 +++++++++++++++++++++++++++++++++------
1 file changed, 44 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index da6e2d8fe3a..4347153d794 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -131,13 +131,47 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt)
#endif
}
+/*
+ * Returns the effective PMM field.
+ *
+ * @env: CPURISCVState
+ *
+ * The PMM field selection logic for each effective privilege mode
+ * is as follows:
+ *
+ * - mstatus.MXR = 1: disabled
+ *
+ * - Smmpm + Smnpm + Ssnpm:
+ * M-mode: mseccfg.PMM
+ * S-mode: menvcfg.PMM
+ * U-mode: senvcfg.PMM
+ * VS-mode: henvcfg.PMM
+ * VU-mode: senvcfg.PMM
+ *
+ * - Smmpm + Smnpm (RVS implemented):
+ * M-mode: mseccfg.PMM
+ * S-mode: menvcfg.PMM
+ * U/VS/VU: disabled (Ssnpm not present)
+ *
+ * - Smmpm + Smnpm (RVS not implemented):
+ * M-mode: mseccfg.PMM
+ * U-mode: menvcfg.PMM
+ * S/VS/VU: disabled (no S-mode)
+ *
+ * - Smmpm only:
+ * M-mode: mseccfg.PMM
+ * Other existing modes: disabled
+ */
RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
{
#ifndef CONFIG_USER_ONLY
- int priv_mode = cpu_address_mode(env);
+ int priv_mode;
+ bool virt;
+
+ riscv_cpu_eff_priv(env, &priv_mode, &virt);
- if (get_field(env->mstatus, MSTATUS_MPRV) &&
- get_field(env->mstatus, MSTATUS_MXR)) {
+ if ((priv_mode != PRV_M && get_field(env->mstatus, MSTATUS_MXR)) ||
+ (virt && get_field(env->vsstatus, MSTATUS_MXR))) {
return PMM_FIELD_DISABLED;
}
@@ -149,12 +183,14 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
}
break;
case PRV_S:
- if (riscv_cpu_cfg(env)->ext_smnpm) {
- if (get_field(env->mstatus, MSTATUS_MPV)) {
- return get_field(env->henvcfg, HENVCFG_PMM);
- } else {
+ if (!virt) {
+ if (riscv_cpu_cfg(env)->ext_smnpm) {
return get_field(env->menvcfg, MENVCFG_PMM);
}
+ } else {
+ if (riscv_cpu_cfg(env)->ext_ssnpm) {
+ return get_field(env->henvcfg, HENVCFG_PMM);
+ }
}
break;
case PRV_U:
@@ -171,6 +207,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
default:
g_assert_not_reached();
}
+
return PMM_FIELD_DISABLED;
#else
return PMM_FIELD_DISABLED;
--
2.43.0
next prev parent reply other threads:[~2025-12-11 16:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-11 16:38 [PATCH v3 0/6] Fix Zjpm implementation frank.chang
2025-12-11 16:38 ` [PATCH v3 1/6] target/riscv: fix address masking frank.chang
2025-12-11 16:38 ` [PATCH v3 2/6] target/riscv: Add a helper to return the current effective priv mode frank.chang
2025-12-11 16:38 ` frank.chang [this message]
2025-12-11 16:38 ` [PATCH v3 4/6] target/riscv: Fix pointer masking for virtual-machine load/store insns frank.chang
2025-12-11 16:38 ` [PATCH v3 5/6] target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm() frank.chang
2025-12-11 16:38 ` [PATCH v3 6/6] target/riscv: Fix pointer masking translation mode check bug frank.chang
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