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[216.71.219.44]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c0c2599228dsm3370410a12.1.2025.12.11.15.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Dec 2025 15:44:33 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eric Auger , qemu-arm@nongnu.org, Tao Tang , Pierrick Bouvier Subject: [PATCH 0/2] target/arm: make granule_protection_check usable from SMMU Date: Thu, 11 Dec 2025 15:44:24 -0800 Message-ID: <20251211234426.2403792-1-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series prepare granule_protection_check to be usable from SMMU, for implementing RME feature. It's based on Tao's commit [1] extracting ARMSecuritySpace from cpu.h header for convenience. [1] https://lore.kernel.org/qemu-devel/20251012150701.4127034-5-tangtao1634@phytium.com.cn/ To demonstrate the purpose, this is the (wip) change to use that from SMMU: diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 80f48df3dda..1acff3bbd66 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1055,12 +1056,36 @@ static SMMUTranslationStatus smmuv3_do_translate(SMMUv3State *s, hwaddr addr, } cached_entry = smmu_translate(bs, cfg, addr, flag, &ptw_info); if (desc_s2_translation) { cfg->asid = asid; cfg->stage = stage; } + if (cached_entry) { + hwaddr paddress = CACHED_ENTRY_TO_ADDR(cached_entry, addr); + ARMSecuritySpace pspace = sec_sid_to_security_space(cfg->sec_sid); + ARMSecuritySpace ss = ARMSS_Root; + ARMMMUFaultInfo fi; + + ARMGranuleProtectionConfig gpc = { + .gpccr = s->root.gpt_base_cfg, + .gptbr = s->root.gpt_base >> 12, + .parange = 6, /* 52 bits */ + .support_sel2 = false, + .as_secure = &s->smmu_state.as_secure_memory + }; + /* The fields in SMMU_ROOT_GPT_BASE_CFG are the same as for GPCCR_EL3, + * except there is no copy of GPCCR_EL3.GPC. See SMMU_ROOT_CR0.GPCEN. */ + const bool gpc_enabled = FIELD_EX32(s->root.cr0, ROOT_CR0, GPCEN); + gpc.gpccr = FIELD_DP64(gpc.gpccr, GPCCR, GPC, gpc_enabled); + bool gpc_check = arm_granule_protection_check(gpc, paddress, + pspace, ss, &fi); + if (!gpc_check) { + printf("ERROR: fi.type=%d fi.gpcf=%d\n", fi.type, fi.gpcf); + g_assert_not_reached(); + } + } + if (!cached_entry) { /* All faults from PTW has S2 field. */ event->u.f_walk_eabt.s2 = (ptw_info.stage == SMMU_STAGE_2); Pierrick Bouvier (1): target/arm/ptw: make granule_protection_check usable without a cpu Tao Tang (1): target/arm: Move ARMSecuritySpace to a common header include/hw/arm/arm-security.h | 54 +++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 39 ++++++++++--------------- target/arm/ptw.c | 41 +++++++++++++++----------- 3 files changed, 93 insertions(+), 41 deletions(-) create mode 100644 include/hw/arm/arm-security.h -- 2.47.3