* [PATCH v2 1/7] target/alpha: Introduce alpha_phys_addr_space_bits()
2025-12-15 19:42 [PATCH v2 0/7] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS Anton Johansson via
@ 2025-12-15 19:42 ` Anton Johansson via
2025-12-15 19:42 ` [PATCH v2 2/7] target/hppa: Define PA[20|1X] physical address space size Anton Johansson via
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Anton Johansson via @ 2025-12-15 19:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Richard Henderson
In preparation for dropping TARGET_PHYS_ADDR_SPACE_BITS, add a
a runtime function to correctly represent the size of the physical
address space for EV4-6 based on the current CPU version.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
linux-user/alpha/target_proc.h | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/linux-user/alpha/target_proc.h b/linux-user/alpha/target_proc.h
index da437ee0e5..6b491ffa3a 100644
--- a/linux-user/alpha/target_proc.h
+++ b/linux-user/alpha/target_proc.h
@@ -6,6 +6,27 @@
#ifndef ALPHA_TARGET_PROC_H
#define ALPHA_TARGET_PROC_H
+#include "qemu/osdep.h"
+#include "target/alpha/cpu.h"
+
+static uint8_t alpha_phys_addr_space_bits(CPUAlphaState *env)
+{
+ switch (env->implver) {
+ case IMPLVER_2106x:
+ /* EV4 */
+ return 34;
+ case IMPLVER_21164:
+ /* EV5 */
+ return 40;
+ case IMPLVER_21264:
+ case IMPLVER_21364:
+ /* EV6 and EV7*/
+ return 44;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static int open_cpuinfo(CPUArchState *cpu_env, int fd)
{
int max_cpus = sysconf(_SC_NPROCESSORS_CONF);
@@ -57,7 +78,7 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
"L1 Dcache\t\t: n/a\n"
"L2 cache\t\t: n/a\n"
"L3 cache\t\t: n/a\n",
- model, TARGET_PAGE_SIZE, TARGET_PHYS_ADDR_SPACE_BITS,
+ model, TARGET_PAGE_SIZE, alpha_phys_addr_space_bits(cpu_env),
max_cpus, num_cpus, cpu_mask);
return 0;
--
2.51.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 2/7] target/hppa: Define PA[20|1X] physical address space size
2025-12-15 19:42 [PATCH v2 0/7] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS Anton Johansson via
2025-12-15 19:42 ` [PATCH v2 1/7] target/alpha: Introduce alpha_phys_addr_space_bits() Anton Johansson via
@ 2025-12-15 19:42 ` Anton Johansson via
2025-12-15 19:42 ` [PATCH v2 3/7] target/i386: Drop physical address range checks Anton Johansson via
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Anton Johansson via @ 2025-12-15 19:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Richard Henderson
When converting virtual to physical addresses,
TARGET_PHYS_ADDR_SPACE_BITS is used under PA-RISC 2.0, and an explicit
cast to uint32_t is used under PA-RISC 1.X. Replace the former with a
more specific macro limited to mem_helper.c, and make the latter
conversion explicit by defining the size of the physical address space
for PA-RISC 1.X.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
target/hppa/mem_helper.c | 23 ++++++++++++++++++-----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index cce82e6599..8563bb0e2a 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -29,6 +29,19 @@
#include "hw/core/cpu.h"
#include "trace.h"
+/*
+ * 64-bit (PA-RISC 2.0) machines are assumed to run PA-8700, and 32-bit
+ * machines 7300LC. This gives 44 and 32 bits of physical address space
+ * respectively.
+ *
+ * CPU model Physical address space bits
+ * PA-7000--7300LC 32
+ * PA-8000--8600 40
+ * PA-8700--8900 44
+ */
+#define HPPA_PHYS_ADDR_SPACE_BITS_PA20 44
+#define HPPA_PHYS_ADDR_SPACE_BITS_PA1X 32
+
hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr)
{
/*
@@ -42,8 +55,8 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr)
* Since the supported physical address space is below 54 bits, the
* H-8 algorithm is moot and all that is left is to truncate.
*/
- QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 54);
- return sextract64(addr, 0, TARGET_PHYS_ADDR_SPACE_BITS);
+ QEMU_BUILD_BUG_ON(HPPA_PHYS_ADDR_SPACE_BITS_PA20 > 54);
+ return sextract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20);
}
hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr)
@@ -67,7 +80,7 @@ hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr)
* is what can be seen on physical machines too.
*/
addr = (uint32_t)addr;
- addr |= -1ull << (TARGET_PHYS_ADDR_SPACE_BITS - 4);
+ addr |= -1ull << (HPPA_PHYS_ADDR_SPACE_BITS_PA20 - 4);
}
return addr;
}
@@ -217,7 +230,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
if (hppa_is_pa20(env)) {
phys = hppa_abs_to_phys_pa2_w0(addr);
} else {
- phys = (uint32_t)addr;
+ phys = extract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA1X);
}
break;
default:
@@ -558,7 +571,7 @@ static void itlbt_pa20(CPUHPPAState *env, target_ulong r1,
/* Align per the page size. */
ent->pa &= TARGET_PAGE_MASK << mask_shift;
/* Ignore the bits beyond physical address space. */
- ent->pa = sextract64(ent->pa, 0, TARGET_PHYS_ADDR_SPACE_BITS);
+ ent->pa = sextract64(ent->pa, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20);
ent->t = extract64(r2, 61, 1);
ent->d = extract64(r2, 60, 1);
--
2.51.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 3/7] target/i386: Drop physical address range checks
2025-12-15 19:42 [PATCH v2 0/7] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS Anton Johansson via
2025-12-15 19:42 ` [PATCH v2 1/7] target/alpha: Introduce alpha_phys_addr_space_bits() Anton Johansson via
2025-12-15 19:42 ` [PATCH v2 2/7] target/hppa: Define PA[20|1X] physical address space size Anton Johansson via
@ 2025-12-15 19:42 ` Anton Johansson via
2025-12-15 19:42 ` [PATCH v2 4/7] target/loongarch: Introduce loongarch_palen_mask() Anton Johansson via
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Anton Johansson via @ 2025-12-15 19:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Richard Henderson
Since TARGET_PHYS_ADDR_SPACE_BITS is now fixed to 64 bits for all
targets we can remove range checks on cpu->phys_bits and
TCG_PHYS_ADDR_BITS.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
target/i386/tcg/helper-tcg.h | 2 --
target/i386/cpu.c | 9 +++------
target/i386/kvm/kvm.c | 3 +--
3 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
index e41cbda407..f4b2ff740d 100644
--- a/target/i386/tcg/helper-tcg.h
+++ b/target/i386/tcg/helper-tcg.h
@@ -31,8 +31,6 @@
# define TCG_PHYS_ADDR_BITS 36
#endif
-QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS);
-
/**
* x86_cpu_do_interrupt:
* @cpu: vCPU the interrupt is to be handled by.
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6417775786..0eeceed7cd 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -9435,12 +9435,9 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
* accel-specific code in cpu_exec_realizefn.
*/
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
- if (cpu->phys_bits &&
- (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
- cpu->phys_bits < 32)) {
- error_setg(errp, "phys-bits should be between 32 and %u "
- " (but is %u)",
- TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
+ if (cpu->phys_bits && cpu->phys_bits < 32) {
+ error_setg(errp, "phys-bits should be at least 32"
+ " (but is %u)", cpu->phys_bits);
return;
}
/*
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 60c7981138..edfff01d64 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -4681,8 +4681,7 @@ static int kvm_get_msrs(X86CPU *cpu)
*/
if (cpu->fill_mtrr_mask) {
- QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
- assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
+ assert(cpu->phys_bits <= 52);
mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
} else {
mtrr_top_bits = 0;
--
2.51.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 4/7] target/loongarch: Introduce loongarch_palen_mask()
2025-12-15 19:42 [PATCH v2 0/7] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS Anton Johansson via
` (2 preceding siblings ...)
2025-12-15 19:42 ` [PATCH v2 3/7] target/i386: Drop physical address range checks Anton Johansson via
@ 2025-12-15 19:42 ` Anton Johansson via
2025-12-15 19:42 ` [PATCH v2 5/7] hw/loongarch: Use loongarch_palen_mask() Anton Johansson via
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Anton Johansson via @ 2025-12-15 19:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Richard Henderson
In preparation for dropping TARGET_PHYS_ADDR_SPACE_BITS, define a
runtime function to construct a mask from the PALEN cpucfg field.
The mask is then used when converting from virtual to physical
addresses.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
target/loongarch/cpu-mmu.h | 1 +
target/loongarch/internals.h | 1 -
target/loongarch/cpu_helper.c | 14 +++++++++++---
target/loongarch/tcg/tlb_helper.c | 12 ++++++++----
4 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h
index 2259de9d36..3286accc14 100644
--- a/target/loongarch/cpu-mmu.h
+++ b/target/loongarch/cpu-mmu.h
@@ -98,5 +98,6 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
uint64_t *dir_width, unsigned int level);
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+uint64_t loongarch_palen_mask(CPULoongArchState *env);
#endif /* LOONGARCH_CPU_MMU_H */
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 8793bd9df6..e01dbed40f 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -13,7 +13,6 @@
#define FCMP_UN 0b0100 /* unordered */
#define FCMP_GT 0b1000 /* fp0 > fp1 */
-#define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS)
#define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
void loongarch_translate_init(void);
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index a6eba4f416..6497b454a6 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -147,6 +147,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
{
CPUState *cs = env_cpu(env);
target_ulong index = 0, phys = 0;
+ uint64_t palen_mask = loongarch_palen_mask(env);
uint64_t dir_base, dir_width;
uint64_t base, pte;
int level;
@@ -154,13 +155,14 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
TLBRet ret;
MemTxResult ret1;
+
address = context->addr;
if ((address >> 63) & 0x1) {
base = env->CSR_PGDH;
} else {
base = env->CSR_PGDL;
}
- base &= TARGET_PHYS_MASK;
+ base &= palen_mask;
for (level = 4; level >= 0; level--) {
get_dir_base_width(env, &dir_base, &dir_width, level);
@@ -181,7 +183,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
break;
} else {
/* Discard high bits with page directory table */
- base &= TARGET_PHYS_MASK;
+ base &= palen_mask;
}
}
}
@@ -315,7 +317,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
/* Check PG and DA */
address = context->addr;
if (da & !pg) {
- context->physical = address & TARGET_PHYS_MASK;
+ context->physical = address & loongarch_palen_mask(env);
context->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
context->mmu_index = MMU_DA_IDX;
return TLBRET_MATCH;
@@ -364,3 +366,9 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
return context.physical;
}
+
+uint64_t loongarch_palen_mask(CPULoongArchState *env)
+{
+ uint64_t phys_bits = FIELD_EX32(env->cpucfg[1], CPUCFG1, PALEN);
+ return MAKE_64BIT_MASK(0, phys_bits);
+}
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 01e0a27f0b..30107f3e3f 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -691,8 +691,10 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
{
CPUState *cs = env_cpu(env);
target_ulong badvaddr, index, phys;
+ uint64_t palen_mask = loongarch_palen_mask(env);
uint64_t dir_base, dir_width;
+
if (unlikely((level == 0) || (level > 4))) {
qemu_log_mask(LOG_GUEST_ERROR,
"Attepted LDDIR with level %u\n", level);
@@ -714,11 +716,11 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
}
badvaddr = env->CSR_TLBRBADV;
- base = base & TARGET_PHYS_MASK;
+ base = base & palen_mask;
get_dir_base_width(env, &dir_base, &dir_width, level);
index = (badvaddr >> dir_base) & ((1 << dir_width) - 1);
phys = base | index << 3;
- return ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
+ return ldq_phys(cs->as, phys) & palen_mask;
}
void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
@@ -728,9 +730,11 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
target_ulong phys, tmp0, ptindex, ptoffset0, ptoffset1, badv;
uint64_t ptbase = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE);
uint64_t ptwidth = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH);
+ uint64_t palen_mask = loongarch_palen_mask(env);
uint64_t dir_base, dir_width;
uint8_t ps;
+
/*
* The parameter "base" has only two types,
* one is the page table base address,
@@ -738,7 +742,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
* and the other is the huge page entry,
* whose bit 6 should be 1.
*/
- base = base & TARGET_PHYS_MASK;
+ base = base & palen_mask;
if (FIELD_EX64(base, TLBENTRY, HUGE)) {
/*
* Gets the huge page level and Gets huge page size.
@@ -779,7 +783,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
ptoffset0 = ptindex << 3;
ptoffset1 = (ptindex + 1) << 3;
phys = base | (odd ? ptoffset1 : ptoffset0);
- tmp0 = ldq_phys(cs->as, phys) & TARGET_PHYS_MASK;
+ tmp0 = ldq_phys(cs->as, phys) & palen_mask;
ps = ptbase;
}
--
2.51.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 5/7] hw/loongarch: Use loongarch_palen_mask()
2025-12-15 19:42 [PATCH v2 0/7] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS Anton Johansson via
` (3 preceding siblings ...)
2025-12-15 19:42 ` [PATCH v2 4/7] target/loongarch: Introduce loongarch_palen_mask() Anton Johansson via
@ 2025-12-15 19:42 ` Anton Johansson via
2025-12-15 19:42 ` [PATCH v2 6/7] hw/riscv: Fix IOMMU PAS capability to 56 bits Anton Johansson via
2025-12-15 19:42 ` [PATCH v2 7/7] Drop TARGET_PHYS_ADDR_SPACE_BITS Anton Johansson via
6 siblings, 0 replies; 8+ messages in thread
From: Anton Johansson via @ 2025-12-15 19:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Richard Henderson
Replaces remaining uses of TARGET_PHYS_ADDR_SPACE_BITS with
runtime calls to loongarch_palen_mask() to fetch the physical
address mask from the cpucfg PALEN field.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/hw/loongarch/boot.h | 3 ++-
hw/loongarch/boot.c | 28 ++++++++++++++++------------
hw/loongarch/virt.c | 5 ++++-
3 files changed, 22 insertions(+), 14 deletions(-)
diff --git a/include/hw/loongarch/boot.h b/include/hw/loongarch/boot.h
index 9819f7fbe3..4984322f75 100644
--- a/include/hw/loongarch/boot.h
+++ b/include/hw/loongarch/boot.h
@@ -113,6 +113,7 @@ struct memmap_entry {
uint32_t reserved;
};
-void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info);
+void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info,
+ uint64_t phys_addr_mask);
#endif /* HW_LOONGARCH_BOOT_H */
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 8857a04998..d18aa575ba 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -217,10 +217,12 @@ static void init_cmdline(struct loongarch_boot_info *info, void *p, void *start)
static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
{
- return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
+ uint64_t *phys_addr_mask = opaque;
+ return addr & *phys_addr_mask;
}
static int64_t load_loongarch_linux_image(const char *filename,
+ uint64_t phys_addr_mask,
uint64_t *kernel_entry,
uint64_t *kernel_low,
uint64_t *kernel_high)
@@ -251,10 +253,8 @@ static int64_t load_loongarch_linux_image(const char *filename,
}
/* Early kernel versions may have those fields in virtual address */
- *kernel_entry = extract64(le64_to_cpu(hdr->kernel_entry),
- 0, TARGET_PHYS_ADDR_SPACE_BITS);
- *kernel_low = extract64(le64_to_cpu(hdr->load_offset),
- 0, TARGET_PHYS_ADDR_SPACE_BITS);
+ *kernel_entry = le64_to_cpu(hdr->kernel_entry) & phys_addr_mask;
+ *kernel_low = le64_to_cpu(hdr->load_offset) & phys_addr_mask;
*kernel_high = *kernel_low + size;
rom_add_blob_fixed(filename, buffer, size, *kernel_low);
@@ -303,19 +303,21 @@ static ram_addr_t alloc_initrd_memory(struct loongarch_boot_info *info,
exit(1);
}
-static int64_t load_kernel_info(struct loongarch_boot_info *info)
+static int64_t load_kernel_info(struct loongarch_boot_info *info,
+ uint64_t phys_addr_mask)
{
uint64_t kernel_entry, kernel_low, kernel_high, initrd_offset = 0;
ssize_t kernel_size;
kernel_size = load_elf(info->kernel_filename, NULL,
- cpu_loongarch_virt_to_phys, NULL,
+ cpu_loongarch_virt_to_phys, &phys_addr_mask,
&kernel_entry, &kernel_low,
&kernel_high, NULL, ELFDATA2LSB,
EM_LOONGARCH, 1, 0);
- kernel_entry = cpu_loongarch_virt_to_phys(NULL, kernel_entry);
+ kernel_entry = cpu_loongarch_virt_to_phys(&phys_addr_mask, kernel_entry);
if (kernel_size < 0) {
kernel_size = load_loongarch_linux_image(info->kernel_filename,
+ phys_addr_mask,
&kernel_entry, &kernel_low,
&kernel_high);
}
@@ -395,14 +397,15 @@ static void init_boot_rom(MachineState *ms,
}
static void loongarch_direct_kernel_boot(MachineState *ms,
- struct loongarch_boot_info *info)
+ struct loongarch_boot_info *info,
+ uint64_t phys_addr_mask)
{
void *p, *bp;
int64_t kernel_addr = VIRT_FLASH0_BASE;
uint64_t *data;
if (info->kernel_filename) {
- kernel_addr = load_kernel_info(info);
+ kernel_addr = load_kernel_info(info, phys_addr_mask);
} else {
if (!qtest_enabled()) {
warn_report("No kernel provided, booting from flash drive.");
@@ -429,7 +432,8 @@ static void loongarch_direct_kernel_boot(MachineState *ms,
g_free(bp);
}
-void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info)
+void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info,
+ uint64_t phys_addr_mask)
{
LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(ms);
@@ -440,6 +444,6 @@ void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info)
if (lvms->bios_loaded) {
loongarch_firmware_boot(lvms, info);
} else {
- loongarch_direct_kernel_boot(ms, info);
+ loongarch_direct_kernel_boot(ms, info, phys_addr_mask);
}
}
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 49434ad182..e3e61903b0 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -33,6 +33,7 @@
#include "hw/misc/unimp.h"
#include "hw/loongarch/fw_cfg.h"
#include "target/loongarch/cpu.h"
+#include "target/loongarch/cpu-mmu.h"
#include "hw/firmware/smbios.h"
#include "qapi/qapi-visit-common.h"
#include "hw/acpi/generic_event_device.h"
@@ -785,6 +786,7 @@ static void virt_init(MachineState *machine)
hwaddr base, size, ram_size = machine->ram_size;
MachineClass *mc = MACHINE_GET_CLASS(machine);
Object *cpuobj;
+ uint64_t phys_addr_mask = 0;
if (!cpu_model) {
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@@ -872,7 +874,8 @@ static void virt_init(MachineState *machine)
qemu_register_powerdown_notifier(&lvms->powerdown_notifier);
lvms->bootinfo.ram_size = ram_size;
- loongarch_load_kernel(machine, &lvms->bootinfo);
+ phys_addr_mask = loongarch_palen_mask(&LOONGARCH_CPU(first_cpu)->env);
+ loongarch_load_kernel(machine, &lvms->bootinfo, phys_addr_mask);
}
static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
--
2.51.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 6/7] hw/riscv: Fix IOMMU PAS capability to 56 bits
2025-12-15 19:42 [PATCH v2 0/7] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS Anton Johansson via
` (4 preceding siblings ...)
2025-12-15 19:42 ` [PATCH v2 5/7] hw/loongarch: Use loongarch_palen_mask() Anton Johansson via
@ 2025-12-15 19:42 ` Anton Johansson via
2025-12-15 19:42 ` [PATCH v2 7/7] Drop TARGET_PHYS_ADDR_SPACE_BITS Anton Johansson via
6 siblings, 0 replies; 8+ messages in thread
From: Anton Johansson via @ 2025-12-15 19:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Richard Henderson
Replaces the only remaining use of TARGET_PHYS_ADDR_SPACE_BITS for RISCV
with the fixed size of the riscv64 physical address space.
Better would be to somehow determine if a 32-bit or 64-bit cpu is
running and set accordingly, but I'm not sure how that would be done
from the device instance init function. This field is unused anyway.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
hw/riscv/riscv-iommu.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index f8656ec04b..573c536824 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -2448,9 +2448,15 @@ static void riscv_iommu_instance_init(Object *obj)
/* Enable translation debug interface */
s->cap = RISCV_IOMMU_CAP_DBG;
- /* Report QEMU target physical address space limits */
- s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,
- TARGET_PHYS_ADDR_SPACE_BITS);
+ /*
+ * Report QEMU target physical address space limits.
+ *
+ * Currently set to the riscv64 limit of 56 bits (44 bit PPN),
+ * riscv32 would use 34 bits (22 bit PPN).
+ *
+ * This field is currently unused.
+ */
+ s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS, 56);
/* TODO: method to report supported PID bits */
s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */
--
2.51.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 7/7] Drop TARGET_PHYS_ADDR_SPACE_BITS
2025-12-15 19:42 [PATCH v2 0/7] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS Anton Johansson via
` (5 preceding siblings ...)
2025-12-15 19:42 ` [PATCH v2 6/7] hw/riscv: Fix IOMMU PAS capability to 56 bits Anton Johansson via
@ 2025-12-15 19:42 ` Anton Johansson via
6 siblings, 0 replies; 8+ messages in thread
From: Anton Johansson via @ 2025-12-15 19:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Richard Henderson, Brian Cain
The macro is no longer in use and can safely be dropped.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu-defs.h | 3 ---
include/exec/poison.h | 2 --
target/alpha/cpu-param.h | 3 ---
target/arm/cpu-param.h | 2 --
target/avr/cpu-param.h | 1 -
target/hexagon/cpu-param.h | 1 -
target/hppa/cpu-param.h | 2 --
target/i386/cpu-param.h | 2 --
target/loongarch/cpu-param.h | 1 -
target/m68k/cpu-param.h | 1 -
target/microblaze/cpu-param.h | 2 --
target/mips/cpu-param.h | 2 --
target/openrisc/cpu-param.h | 1 -
target/ppc/cpu-param.h | 7 -------
target/riscv/cpu-param.h | 2 --
target/rx/cpu-param.h | 1 -
target/s390x/cpu-param.h | 1 -
target/sh4/cpu-param.h | 1 -
target/sparc/cpu-param.h | 2 --
target/tricore/cpu-param.h | 1 -
target/xtensa/cpu-param.h | 1 -
21 files changed, 39 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index e01acb7c90..141b5a9929 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -28,9 +28,6 @@
#ifndef TARGET_LONG_BITS
# error TARGET_LONG_BITS must be defined in cpu-param.h
#endif
-#ifndef TARGET_PHYS_ADDR_SPACE_BITS
-# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h
-#endif
#ifndef TARGET_VIRT_ADDR_SPACE_BITS
# error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h
#endif
diff --git a/include/exec/poison.h b/include/exec/poison.h
index a779adbb7a..2caf2d92f1 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -43,8 +43,6 @@
#pragma GCC poison TARGET_FMT_ld
#pragma GCC poison TARGET_FMT_lu
-#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS
-
#pragma GCC poison CONFIG_ALPHA_DIS
#pragma GCC poison CONFIG_HPPA_DIS
#pragma GCC poison CONFIG_I386_DIS
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index a799f42db3..e04bfeee12 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -8,9 +8,6 @@
#ifndef ALPHA_CPU_PARAM_H
#define ALPHA_CPU_PARAM_H
-/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
-#define TARGET_PHYS_ADDR_SPACE_BITS 44
-
#ifdef CONFIG_USER_ONLY
/*
* Allow user-only to vary page size. Real hardware allows only 8k and 64k,
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 8b46c7c570..08785125ad 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -9,10 +9,8 @@
#define ARM_CPU_PARAM_H
#ifdef TARGET_AARCH64
-# define TARGET_PHYS_ADDR_SPACE_BITS 52
# define TARGET_VIRT_ADDR_SPACE_BITS 52
#else
-# define TARGET_PHYS_ADDR_SPACE_BITS 40
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index f74bfc2580..066ada1e9c 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -22,7 +22,6 @@
#define AVR_CPU_PARAM_H
#define TARGET_PAGE_BITS 10
-#define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24
#define TARGET_INSN_START_EXTRA_WORDS 0
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 635d509e74..31da1a239f 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -20,7 +20,6 @@
#define TARGET_PAGE_BITS 16 /* 64K pages */
-#define TARGET_PHYS_ADDR_SPACE_BITS 36
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_INSN_START_EXTRA_WORDS 0
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index 9bf7ac76d0..8e33d1ac36 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -9,11 +9,9 @@
#define HPPA_CPU_PARAM_H
#if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32)
-# define TARGET_PHYS_ADDR_SPACE_BITS 32
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#else
/* ??? PA-8000 through 8600 have 40 bits; PA-8700 and 8900 have 44 bits. */
-# define TARGET_PHYS_ADDR_SPACE_BITS 40
# define TARGET_VIRT_ADDR_SPACE_BITS 64
#endif
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index ebb844bcc8..9e4cb74e04 100644
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -9,7 +9,6 @@
#define I386_CPU_PARAM_H
#ifdef TARGET_X86_64
-# define TARGET_PHYS_ADDR_SPACE_BITS 52
/*
* ??? This is really 48 bits, sign-extended, but the only thing
* accessible to userland with bit 48 set is the VSYSCALL, and that
@@ -17,7 +16,6 @@
*/
# define TARGET_VIRT_ADDR_SPACE_BITS 47
#else
-# define TARGET_PHYS_ADDR_SPACE_BITS 36
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define TARGET_PAGE_BITS 12
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index 58cc45a377..7779461054 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -8,7 +8,6 @@
#ifndef LOONGARCH_CPU_PARAM_H
#define LOONGARCH_CPU_PARAM_H
-#define TARGET_PHYS_ADDR_SPACE_BITS 48
#define TARGET_VIRT_ADDR_SPACE_BITS 48
#define TARGET_PAGE_BITS 12
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 256a2b5f8b..802d8fc674 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -14,7 +14,6 @@
* use the smallest one
*/
#define TARGET_PAGE_BITS 12
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_INSN_START_EXTRA_WORDS 1
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index e0a3794513..90a0cf2435 100644
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -17,10 +17,8 @@
* of address space.
*/
#ifdef CONFIG_USER_ONLY
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#else
-#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
#endif
diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h
index 58f450827f..d62110e732 100644
--- a/target/mips/cpu-param.h
+++ b/target/mips/cpu-param.h
@@ -8,10 +8,8 @@
#define MIPS_CPU_PARAM_H
#ifdef TARGET_ABI_MIPSN64
-#define TARGET_PHYS_ADDR_SPACE_BITS 48
#define TARGET_VIRT_ADDR_SPACE_BITS 48
#else
-#define TARGET_PHYS_ADDR_SPACE_BITS 40
# ifdef CONFIG_USER_ONLY
# define TARGET_VIRT_ADDR_SPACE_BITS 31
# else
diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h
index b4f57bbe69..740cf76ddd 100644
--- a/target/openrisc/cpu-param.h
+++ b/target/openrisc/cpu-param.h
@@ -9,7 +9,6 @@
#define OPENRISC_CPU_PARAM_H
#define TARGET_PAGE_BITS 13
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_INSN_START_EXTRA_WORDS 1
diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h
index e4ed9080ee..2065915dc5 100644
--- a/target/ppc/cpu-param.h
+++ b/target/ppc/cpu-param.h
@@ -9,12 +9,6 @@
#define PPC_CPU_PARAM_H
#ifdef TARGET_PPC64
-/*
- * Note that the official physical address space bits is 62-M where M
- * is implementation dependent. I've not looked up M for the set of
- * cpus we emulate at the system level.
- */
-#define TARGET_PHYS_ADDR_SPACE_BITS 62
/*
* Note that the PPC environment architecture talks about 80 bit virtual
* addresses, with segmentation. Obviously that's not all visible to a
@@ -26,7 +20,6 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 64
# endif
#else
-# define TARGET_PHYS_ADDR_SPACE_BITS 36
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index cfdc67c258..b96e1ce12e 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -9,10 +9,8 @@
#define RISCV_CPU_PARAM_H
#if defined(TARGET_RISCV64)
-# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
#elif defined(TARGET_RISCV32)
-# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h
index 84934f3bca..4cf6183aa0 100644
--- a/target/rx/cpu-param.h
+++ b/target/rx/cpu-param.h
@@ -21,7 +21,6 @@
#define TARGET_PAGE_BITS 12
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_INSN_START_EXTRA_WORDS 0
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index abfae3bedf..e46e0757c6 100644
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -9,7 +9,6 @@
#define S390_CPU_PARAM_H
#define TARGET_PAGE_BITS 12
-#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
#define TARGET_INSN_START_EXTRA_WORDS 2
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index f328715ee8..e2632bb20f 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -9,7 +9,6 @@
#define SH4_CPU_PARAM_H
#define TARGET_PAGE_BITS 12 /* 4k */
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
#ifdef CONFIG_USER_ONLY
# define TARGET_VIRT_ADDR_SPACE_BITS 31
#else
diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
index 45eea9d6ba..4c92862ea3 100644
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@@ -9,7 +9,6 @@
#ifdef TARGET_SPARC64
# define TARGET_PAGE_BITS 13 /* 8k */
-# define TARGET_PHYS_ADDR_SPACE_BITS 41
# ifdef TARGET_ABI32
# define TARGET_VIRT_ADDR_SPACE_BITS 32
# else
@@ -17,7 +16,6 @@
# endif
#else
# define TARGET_PAGE_BITS 12 /* 4k */
-# define TARGET_PHYS_ADDR_SPACE_BITS 36
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
index eb33a67c41..f260a888c2 100644
--- a/target/tricore/cpu-param.h
+++ b/target/tricore/cpu-param.h
@@ -9,7 +9,6 @@
#define TRICORE_CPU_PARAM_H
#define TARGET_PAGE_BITS 14
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define TARGET_INSN_START_EXTRA_WORDS 0
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
index 7a0c22c900..328176281e 100644
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@@ -9,7 +9,6 @@
#define XTENSA_CPU_PARAM_H
#define TARGET_PAGE_BITS 12
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
#ifdef CONFIG_USER_ONLY
#define TARGET_VIRT_ADDR_SPACE_BITS 30
#else
--
2.51.0
^ permalink raw reply related [flat|nested] 8+ messages in thread