[PATCH v2 00/11] i386/cpu: Add new instructions & CPU model for Intel Diamond Rapids

[Zhao Liu <zhao1.liu@intel.com>]

Hi,

This series addes new instrucions and CPU model support for Intel
Diamond Rapids.

This series mainly includes:
 * MOVRS CPUID
 * new AMX CPUIDs
 * AVX10.2 & AVX10_VNNI_INT
 * DMR CPU model & topology documentation
   - The on-going cache-aware scheduling work could benefit such
     topology:
     https://lore.kernel.org/lkml/cover.1764801860.git.tim.c.chen@linux.intel.com/

This series is based on https://gitlab.com/bonzini/qemu i386 branch at
7c7e2f410b3d ("target/i386/tcg: mark APX as supported").

Compared with v1, v2 mainly did:
 * allow upsupported avx10 version when x-force-feature=on, for debug.
 * rename CPUID_7_1_EDX_APX to CPUID_7_1_EDX_APXF in DMR CPU model.


One More Thing
==============

About the AVX10 model (patch 4), in principle, AVX10.1 should be allowed
to run on an AVX10.2 host. For similar version drived features,
introducing a model might be a preferable way. However, PMU doesn't
serve as a good example here.


Thanks for your review!

Best Regards,
Zhao
---
Zhao Liu (11):
  i386/cpu: Add support for MOVRS in CPUID enumeration
  i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions
  i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration
  i386/cpu: Support AVX10.2 with AVX10 feature models
  i386/cpu: Add a helper to get host avx10 version
  i386/cpu: Allow unsupported avx10_version with x-force-features
  i386/cpu: Allow cache to be shared at thread level
  i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f
  i386/cpu: Define dependency for VMX_VM_ENTRY_LOAD_IA32_FRED
  i386/cpu: Add CPU model for Diamond Rapids
  dosc/cpu-models-x86: Add documentation for DiamondRapids

 docs/system/cpu-models-x86.rst.inc |  20 ++
 target/i386/cpu.c                  | 462 +++++++++++++++++++++++++----
 target/i386/cpu.h                  |  27 ++
 3 files changed, 456 insertions(+), 53 deletions(-)

-- 
2.34.1