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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 11/65] hw/intc/arm_gicv5: Implement gicv5_class_name()
Date: Mon, 23 Feb 2026 17:01:18 +0000	[thread overview]
Message-ID: <20260223170212.441276-12-peter.maydell@linaro.org> (raw)
In-Reply-To: <20260223170212.441276-1-peter.maydell@linaro.org>

Implement a gicv5_class_name() function that does the same job as
gicv3_class_name(): allows board code to get the correct QOM type for
the GIC at runtime depending on whether KVM is enabled or not.

For the GICv5, we don't yet implement KVM support, so the KVM-enabled
codepath is always an error.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv5_common.c         | 12 ++++++++++++
 include/hw/intc/arm_gicv5_common.h | 10 ++++++++++
 2 files changed, 22 insertions(+)

diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c
index 274d8cd255..620ae3b88f 100644
--- a/hw/intc/arm_gicv5_common.c
+++ b/hw/intc/arm_gicv5_common.c
@@ -11,6 +11,8 @@
 #include "hw/core/qdev-properties.h"
 #include "qapi/error.h"
 #include "trace.h"
+#include "qemu/error-report.h"
+#include "system/kvm.h"
 
 OBJECT_DEFINE_ABSTRACT_TYPE(GICv5Common, gicv5_common, ARM_GICV5_COMMON, SYS_BUS_DEVICE)
 
@@ -157,3 +159,13 @@ static void gicv5_common_class_init(ObjectClass *oc, const void *data)
     dc->realize = gicv5_common_realize;
     device_class_set_props(dc, arm_gicv5_common_properties);
 }
+
+const char *gicv5_class_name(void)
+{
+    /* When we implement KVM GICv5 we might return "kvm-arm-gicv5" here. */
+    if (kvm_enabled()) {
+        error_report("Userspace GICv5 is not supported with KVM");
+        exit(1);
+    }
+    return "arm-gicv5";
+}
diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5_common.h
index 3bffa2cb1d..7db2c87ddc 100644
--- a/include/hw/intc/arm_gicv5_common.h
+++ b/include/hw/intc/arm_gicv5_common.h
@@ -150,4 +150,14 @@ static inline bool gicv5_domain_implemented(GICv5Common *cs, GICv5Domain domain)
     return cs->implemented_domains & (1 << domain);
 }
 
+/**
+ * gicv5_class_name
+ *
+ * Return name of GICv5 class to use depending on whether KVM acceleration is
+ * in use. May throw an error if the chosen implementation is not available.
+ *
+ * Returns: class name to use
+ */
+const char *gicv5_class_name(void);
+
 #endif
-- 
2.43.0



  parent reply	other threads:[~2026-02-23 17:11 UTC|newest]

Thread overview: 142+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-23 17:01 [PATCH 00/65] arm: Implement an emulation of GICv5 interrupt controller Peter Maydell
2026-02-23 17:01 ` [PATCH 01/65] hw/core: Permit devices to define an array of link properties Peter Maydell
2026-03-06 11:11   ` Jonathan Cameron via qemu development
2026-03-06 11:17     ` Peter Maydell
2026-03-21 15:42   ` Philippe Mathieu-Daudé
2026-03-23 13:26     ` Peter Maydell
2026-02-23 17:01 ` [PATCH 02/65] hw/intc: Skeleton of GICv5 IRS classes Peter Maydell
2026-03-06 11:15   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 03/65] hw/arm/Kconfig: select ARM_GICV5 for ARM_VIRT board Peter Maydell
2026-03-06 11:16   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 04/65] hw/intc/arm_gicv5: Implement skeleton code for IRS register frames Peter Maydell
2026-03-06 11:51   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 05/65] hw/intc/arm_gicv5: Add migration blocker Peter Maydell
2026-03-06 11:52   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 06/65] hw/intc/arm_gicv5: Create and validate QOM properties Peter Maydell
2026-03-06 12:07   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 07/65] hw/intc/arm_gicv5: Create inbound GPIO lines for SPIs Peter Maydell
2026-03-06 14:57   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 08/65] hw/intc/arm_gicv5: Define macros for config frame registers Peter Maydell
2026-03-06 15:53   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 09/65] hw/intc/arm_gicv5: Implement IRS ID regs Peter Maydell
2026-03-06 16:16   ` Jonathan Cameron via qemu development
2026-03-19 13:22     ` Peter Maydell
2026-02-23 17:01 ` [PATCH 10/65] hw/intc/arm_gicv5: Add link property for MemoryRegion for DMA Peter Maydell
2026-03-06 16:17   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` Peter Maydell [this message]
2026-03-06 17:00   ` [PATCH 11/65] hw/intc/arm_gicv5: Implement gicv5_class_name() Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 12/65] hw/intc/arm_gicv5: Add defines for GICv5 architected PPIs Peter Maydell
2026-03-06 17:09   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 13/65] target/arm: GICv5 cpuif: Initial skeleton and GSB barrier insns Peter Maydell
2026-03-06 17:23   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 14/65] target/arm: Set up pointer to GICv5 in each CPU Peter Maydell
2026-03-06 17:29   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 15/65] hw/intc/arm_gicv5: Implement IRS_IST_{BASER, STATUSR, CFGR} Peter Maydell
2026-03-06 17:39   ` Jonathan Cameron via qemu development
2026-03-06 18:27     ` Peter Maydell
2026-02-23 17:01 ` [PATCH 16/65] hw/intc/arm_gicv5: Cache LPI IST config in a struct Peter Maydell
2026-03-06 17:46   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 17/65] hw/intc/arm_gicv5: Implement gicv5_set_priority() Peter Maydell
2026-03-06 18:02   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 18/65] target/arm: GICv5 cpuif: Implement the GIC CDPRI instruction Peter Maydell
2026-03-06 18:05   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 19/65] hw/intc/arm_gicv5: Implement IRS_MAP_L2_ISTR Peter Maydell
2026-03-06 18:10   ` Jonathan Cameron via qemu development
2026-03-06 18:21     ` Peter Maydell
2026-02-23 17:01 ` [PATCH 20/65] hw/intc/arm_gicv5: Implement remaining set-config functions Peter Maydell
2026-03-11 14:15   ` Jonathan Cameron via qemu development
2026-03-19  9:59     ` Peter Maydell
2026-02-23 17:01 ` [PATCH 21/65] target/arm: GICv5 cpuif: Implement GIC CD* insns for setting config Peter Maydell
2026-03-11 14:24   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 22/65] hw/intc/arm_gicv5: Create backing state for SPIs Peter Maydell
2026-03-11 14:30   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 23/65] hw/intc/arm_gicv5: Make gicv5_set_* update SPI state Peter Maydell
2026-03-11 14:35   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 24/65] hw/intc/arm_gicv5: Implement gicv5_request_config() Peter Maydell
2026-03-11 14:44   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 25/65] target/arm: GICv5 cpuif: Implement GIC CDRCFG and ICC_ICSR_EL1 Peter Maydell
2026-03-11 14:51   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 26/65] hw/intc/arm_gicv5: Implement IRS_SPI_{SELR, STATUSR, CFGR, DOMAINR} Peter Maydell
2026-03-11 15:01   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 27/65] hw/intc/arm_gicv5: Update SPI state for CLEAR/SET events Peter Maydell
2026-03-11 15:23   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 28/65] hw/intc/arm_gicv5: Implement IRS_CR0 and IRS_CR1 Peter Maydell
2026-03-11 15:28   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 29/65] hw/intc/arm_gicv5: Implement IRS_SYNCR and IRS_SYNC_STATUSR Peter Maydell
2026-03-11 15:29   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 30/65] hw/intc/arm_gicv5: Implement IRS_PE_{CR0,SELR,STATUSR} Peter Maydell
2026-03-11 15:31   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 31/65] hw/intc/arm_gicv5: Implement CoreSight ID registers Peter Maydell
2026-02-23 17:01 ` [PATCH 32/65] hw/intc/arm_gicv5: Cache pending LPIs in a hash table Peter Maydell
2026-03-11 15:46   ` Jonathan Cameron via qemu development
2026-03-19 10:11     ` Peter Maydell
2026-02-23 17:01 ` [PATCH 33/65] target/arm: GICv5 cpuif: Implement ICC_IAFFIDR_EL1 Peter Maydell
2026-03-11 15:48   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 34/65] target/arm: GICv5 cpuif: Implement ICC_IDR0_EL1 Peter Maydell
2026-03-11 15:50   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 35/65] target/arm: GICv5 cpuif: Implement GICv5 PPI active set/clear registers Peter Maydell
2026-03-11 16:26   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 36/65] target/arm: GICv5 cpuif: Implement PPI handling mode register Peter Maydell
2026-03-11 16:29   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 37/65] target/arm: GICv5 cpuif: Implement PPI pending status registers Peter Maydell
2026-03-11 16:31   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 38/65] target/arm: GICv5 cpuif: Implement PPI enable register Peter Maydell
2026-03-11 16:32   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 39/65] target/arm: GICv5 cpuif: Implement PPI priority registers Peter Maydell
2026-03-11 16:34   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 40/65] target/arm: GICv5 cpuif: Implement ICC_APR_EL1 and ICC_HAPR_EL1 Peter Maydell
2026-03-11 16:41   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 41/65] target/arm: GICv5 cpuif: Calculate the highest priority PPI Peter Maydell
2026-03-11 16:51   ` Jonathan Cameron via qemu development
2026-03-11 17:08     ` Peter Maydell
2026-03-11 17:39       ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 42/65] hw/intc/arm_gicv5: Calculate HPPI in the IRS Peter Maydell
2026-03-11 16:59   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 43/65] target/arm: GICv5 cpuif: Implement ICC_CR0_EL1 Peter Maydell
2026-03-11 17:01   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 44/65] target/arm: GICv5 cpuif: Implement ICC_PCR_EL1 Peter Maydell
2026-03-11 17:04   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 45/65] target/arm: GICv5 cpuif: Implement ICC_HPPIR_EL1 Peter Maydell
2026-03-11 17:14   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 46/65] hw/intc/arm_gicv5: Implement Activate command Peter Maydell
2026-03-11 17:22   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 47/65] target/arm: GICv5 cpuif: Implement GICR CDIA command Peter Maydell
2026-03-11 17:28   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 48/65] target/arm: GICv5 cpuif: Implement GIC CDEOI Peter Maydell
2026-03-11 17:32   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 49/65] hw/intc/arm_gicv5: Implement Deactivate command Peter Maydell
2026-03-11 17:34   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 50/65] target/arm: GICv5 cpuif: Implement GIC CDDI Peter Maydell
2026-03-11 17:35   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 51/65] target/arm: GICv5 cpuif: Signal IRQ or FIQ Peter Maydell
2026-03-11 17:43   ` Jonathan Cameron via qemu development
2026-02-23 17:01 ` [PATCH 52/65] target/arm: Connect internal interrupt sources up as GICv5 PPIs Peter Maydell
2026-03-11 17:48   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 53/65] target/arm: Add has_gcie property to enable FEAT_GCIE Peter Maydell
2026-03-11 17:51   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 54/65] hw/intc/arm_gicv3_cpuif: Don't allow GICv3 if CPU has GICv5 cpuif Peter Maydell
2026-03-11 17:52   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 55/65] hw/arm/virt: Update error message for bad gic-version option Peter Maydell
2026-03-11 17:54   ` Jonathan Cameron via qemu development
2026-03-12  9:12     ` Peter Maydell
2026-02-23 17:02 ` [PATCH 56/65] hw/arm/virt: Remember CPU phandles rather than looking them up by name Peter Maydell
2026-03-11 17:56   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 57/65] hw/arm/virt: Move MSI controller creation out of create_gic() Peter Maydell
2026-03-11 17:57   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 58/65] hw/arm/virt: Pull "wire CPU interrupts" " Peter Maydell
2026-03-11 18:01   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 59/65] hw/arm/virt: Split GICv2 and GICv3/4 creation Peter Maydell
2026-03-12 13:59   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 60/65] hw/arm/virt: Create and connect GICv5 Peter Maydell
2026-03-12 14:06   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 61/65] hw/arm/virt: Advertise GICv5 in the DTB Peter Maydell
2026-03-12 14:23   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 62/65] hw/arm/virt: Handle GICv5 in interrupt bindings for PPIs Peter Maydell
2026-03-12 14:28   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 63/65] hw/arm/virt: Use correct interrupt type for GICv5 SPIs in the DTB Peter Maydell
2026-03-12 14:29   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 64/65] hw/arm/virt: Enable GICv5 CPU interface when using GICv5 Peter Maydell
2026-03-12 14:32   ` Jonathan Cameron via qemu development
2026-02-23 17:02 ` [PATCH 65/65] hw/arm/virt: Allow user to select GICv5 Peter Maydell
2026-03-12 14:36   ` Jonathan Cameron via qemu development
2026-02-23 17:24 ` [PATCH 00/65] arm: Implement an emulation of GICv5 interrupt controller Peter Maydell

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