From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, philmd@linaro.org,
ltaylorsimpson@gmail.com, matheus.bernardino@oss.qualcomm.com,
marco.liebel@oss.qualcomm.com, quic_mburton@quicinc.com,
sid.manning@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng,
Brian Cain <bcain@quicinc.com>
Subject: [PATCH v5 24/35] target/hexagon: Add sysemu TCG overrides
Date: Tue, 10 Mar 2026 20:49:12 -0700 [thread overview]
Message-ID: <20260311034923.1044737-25-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20260311034923.1044737-1-brian.cain@oss.qualcomm.com>
From: Brian Cain <bcain@quicinc.com>
Define TCG overrides for setprio(), crswap(,sgp{0,1,1:0}).
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/cpu_helper.h | 18 ++++++++++++++++
target/hexagon/gen_tcg_sys.h | 40 ++++++++++++++++++++++++++++++++++++
target/hexagon/helper.h | 1 +
target/hexagon/genptr.c | 4 ++++
target/hexagon/op_helper.c | 10 ++++++++-
target/hexagon/hex_common.py | 2 ++
target/hexagon/meson.build | 13 ++++++------
7 files changed, 81 insertions(+), 7 deletions(-)
create mode 100644 target/hexagon/cpu_helper.h
create mode 100644 target/hexagon/gen_tcg_sys.h
diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h
new file mode 100644
index 00000000000..1486a03c64a
--- /dev/null
+++ b/target/hexagon/cpu_helper.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HEXAGON_CPU_HELPER_H
+#define HEXAGON_CPU_HELPER_H
+
+uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index);
+uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env);
+uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env);
+uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env);
+void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t);
+void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t);
+void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t);
+
+#endif
diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h
new file mode 100644
index 00000000000..04549831ea5
--- /dev/null
+++ b/target/hexagon/gen_tcg_sys.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HEXAGON_GEN_TCG_SYS_H
+#define HEXAGON_GEN_TCG_SYS_H
+
+#define fGEN_TCG_Y2_setprio(SHORTCODE) \
+ gen_helper_setprio(tcg_env, PtV, RsV)
+
+#define fGEN_TCG_Y2_crswap0(SHORTCODE) \
+ do { \
+ TCGv_i32 tmp = tcg_temp_new_i32(); \
+ tcg_gen_mov_tl(tmp, RxV); \
+ tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP0]); \
+ tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP0], tmp); \
+ } while (0)
+
+#define fGEN_TCG_Y4_crswap1(SHORTCODE) \
+ do { \
+ TCGv_i32 tmp = tcg_temp_new_i32(); \
+ tcg_gen_mov_tl(tmp, RxV); \
+ tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP1]); \
+ tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \
+ } while (0)
+
+#define fGEN_TCG_Y4_crswap10(SHORTCODE) \
+ do { \
+ TCGv_i64 tmp = tcg_temp_new_i64(); \
+ tcg_gen_mov_i64(tmp, RxxV); \
+ tcg_gen_concat_i32_i64(RxxV, \
+ hex_t_sreg[HEX_SREG_SGP0], \
+ hex_t_sreg[HEX_SREG_SGP1]); \
+ tcg_gen_extrl_i64_i32(ctx->t_sreg_new_value[HEX_SREG_SGP0], tmp); \
+ tcg_gen_extrh_i64_i32(ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \
+ } while (0)
+
+#endif
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 28b9b59e0f2..5405342f798 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -114,4 +114,5 @@ DEF_HELPER_2(sreg_read_pair, i64, env, i32)
DEF_HELPER_2(greg_read, i32, env, i32)
DEF_HELPER_2(greg_read_pair, i64, env, i32)
DEF_HELPER_3(sreg_write_masked, void, env, i32, i32)
+DEF_HELPER_3(setprio, void, env, i32, i32)
#endif
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 2310b9aec3a..bac63a42def 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -31,6 +31,10 @@
#undef QEMU_GENERATE
#include "gen_tcg.h"
#include "gen_tcg_hvx.h"
+#ifndef CONFIG_USER_ONLY
+#include "gen_tcg_sys.h"
+#endif
+
#include "genptr.h"
TCGv gen_read_reg(TCGv result, int num)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 327c233c01b..d9d84f05553 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -19,9 +19,10 @@
#include "qemu/log.h"
#include "accel/tcg/cpu-ldst.h"
#include "accel/tcg/probe.h"
+#include "qemu/main-loop.h"
+#include "cpu.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
-#include "cpu.h"
#include "internal.h"
#include "macros.h"
#include "sys_macros.h"
@@ -31,6 +32,7 @@
#include "mmvec/mmvec.h"
#include "mmvec/macros.h"
#include "op_helper.h"
+#include "cpu_helper.h"
#include "translate.h"
#ifndef CONFIG_USER_ONLY
#include "hexswi.h"
@@ -1412,6 +1414,12 @@ uint64_t HELPER(greg_read_pair)(CPUHexagonState *env, uint32_t reg)
{
g_assert_not_reached();
}
+
+void HELPER(setprio)(CPUHexagonState *env, uint32_t thread, uint32_t prio)
+{
+ g_assert_not_reached();
+}
+
#endif
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index f7ca4986ca8..3ba1a4523f1 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -1369,6 +1369,7 @@ def parse_common_args(desc):
parser.add_argument("semantics", help="semantics file")
parser.add_argument("overrides", help="overrides file")
parser.add_argument("overrides_vec", help="vector overrides file")
+ parser.add_argument("overrides_sys", help="system overrides file")
parser.add_argument("out", help="output file")
parser.add_argument("--idef-parser",
help="file of instructions translated by idef-parser")
@@ -1376,6 +1377,7 @@ def parse_common_args(desc):
read_semantics_file(args.semantics)
read_overrides_file(args.overrides)
read_overrides_file(args.overrides_vec)
+ read_overrides_file(args.overrides_sys)
if args.idef_parser:
read_idef_parser_enabled_file(args.idef_parser)
calculate_attribs()
diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build
index d169cf71b2f..528beca3cd0 100644
--- a/target/hexagon/meson.build
+++ b/target/hexagon/meson.build
@@ -20,6 +20,7 @@ hexagon_ss = ss.source_set()
hex_common_py = 'hex_common.py'
gen_tcg_h = meson.current_source_dir() / 'gen_tcg.h'
gen_tcg_hvx_h = meson.current_source_dir() / 'gen_tcg_hvx.h'
+gen_tcg_sys_h = meson.current_source_dir() / 'gen_tcg_sys.h'
idef_parser_dir = meson.current_source_dir() / 'idef-parser'
#
@@ -337,12 +338,12 @@ if idef_parser_enabled and 'hexagon-linux-user' in target_dirs
# Setup input and dependencies for the next step, this depends on whether or
# not idef-parser is enabled
helper_dep = [semantics_generated, idef_generated_tcg_c, idef_generated_tcg]
- helper_in = [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, '--idef-parser', idef_generated_list]
+ helper_in = [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h, '--idef-parser', idef_generated_list]
else
# Setup input and dependencies for the next step, this depends on whether or
# not idef-parser is enabled
helper_dep = [semantics_generated]
- helper_in = [semantics_generated, gen_tcg_h, gen_tcg_hvx_h]
+ helper_in = [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h]
endif
#
@@ -356,7 +357,7 @@ helper_protos_generated = custom_target(
'helper_protos_generated.h.inc',
output: 'helper_protos_generated.h.inc',
depends: helper_dep,
- depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h],
+ depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h],
command: [python, files('gen_helper_protos.py'), helper_in, '@OUTPUT@'],
)
hexagon_ss.add(helper_protos_generated)
@@ -365,7 +366,7 @@ helper_funcs_generated = custom_target(
'helper_funcs_generated.c.inc',
output: 'helper_funcs_generated.c.inc',
depends: helper_dep,
- depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h],
+ depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h],
command: [python, files('gen_helper_funcs.py'), helper_in, '@OUTPUT@'],
)
hexagon_ss.add(helper_funcs_generated)
@@ -374,7 +375,7 @@ tcg_funcs_generated = custom_target(
'tcg_funcs_generated.c.inc',
output: 'tcg_funcs_generated.c.inc',
depends: helper_dep,
- depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h],
+ depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h],
command: [python, files('gen_tcg_funcs.py'), helper_in, '@OUTPUT@'],
)
hexagon_ss.add(tcg_funcs_generated)
@@ -383,7 +384,7 @@ analyze_funcs_generated = custom_target(
'analyze_funcs_generated.c.inc',
output: 'analyze_funcs_generated.c.inc',
depends: helper_dep,
- depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h],
+ depend_files: [hex_common_py, gen_tcg_h, gen_tcg_hvx_h, gen_tcg_sys_h],
command: [python, files('gen_analyze_funcs.py'), helper_in, '@OUTPUT@'],
)
hexagon_ss.add(analyze_funcs_generated)
--
2.34.1
next prev parent reply other threads:[~2026-03-11 3:51 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-11 3:48 [PATCH v5 00/35] Hexagon system emulation, Part 1/3 Brian Cain
2026-03-11 3:48 ` [PATCH v5 01/35] docs: Add hexagon sysemu docs Brian Cain
2026-03-11 3:48 ` [PATCH v5 02/35] docs/system: Add hexagon CPU emulation Brian Cain
2026-03-11 3:48 ` [PATCH v5 03/35] target/hexagon: Fix badva reference, delete CAUSE Brian Cain
2026-03-11 3:48 ` [PATCH v5 04/35] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof Brian Cain
2026-03-11 3:48 ` [PATCH v5 05/35] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py Brian Cain
2026-03-11 3:48 ` [PATCH v5 06/35] target/hexagon: Suppress unused-variable warnings for sysemu source regs Brian Cain
2026-03-12 21:03 ` Taylor Simpson
2026-03-11 3:48 ` [PATCH v5 07/35] target/hexagon: Make gen_exception_end_tb non-static Brian Cain
2026-03-11 3:48 ` [PATCH v5 08/35] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain via qemu development
2026-03-11 3:48 ` [PATCH v5 09/35] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2026-03-11 3:48 ` [PATCH v5 10/35] target/hexagon: Add a placeholder fp exception Brian Cain
2026-03-11 3:48 ` [PATCH v5 11/35] target/hexagon: Add guest, system reg number defs Brian Cain
2026-03-11 3:49 ` [PATCH v5 12/35] target/hexagon: Add guest, system reg number state Brian Cain
2026-03-11 3:49 ` [PATCH v5 13/35] target/hexagon: Add TCG values for sreg, greg Brian Cain
2026-03-11 3:49 ` [PATCH v5 14/35] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2026-03-11 3:49 ` [PATCH v5 15/35] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2026-03-11 3:49 ` [PATCH v5 16/35] target/hexagon: Add new macro definitions " Brian Cain
2026-03-11 3:49 ` [PATCH v5 17/35] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2026-03-11 3:49 ` [PATCH v5 18/35] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2026-03-11 3:49 ` [PATCH v5 19/35] target/hexagon: Add vmstate representation Brian Cain
2026-03-25 19:21 ` Philippe Mathieu-Daudé
2026-03-11 3:49 ` [PATCH v5 20/35] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2026-03-11 3:49 ` [PATCH v5 21/35] target/hexagon: Define register fields for system regs Brian Cain
2026-03-11 3:49 ` [PATCH v5 22/35] target/hexagon: Implement do_raise_exception() Brian Cain
2026-03-11 3:49 ` [PATCH v5 23/35] target/hexagon: Add system reg insns Brian Cain
2026-03-11 3:49 ` Brian Cain [this message]
2026-03-25 19:24 ` [PATCH v5 24/35] target/hexagon: Add sysemu TCG overrides Philippe Mathieu-Daudé
2026-03-11 3:49 ` [PATCH v5 25/35] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2026-03-11 3:49 ` [PATCH v5 26/35] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2026-03-11 3:49 ` [PATCH v5 27/35] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2026-03-11 3:49 ` [PATCH v5 28/35] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2026-03-11 3:49 ` [PATCH v5 29/35] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2026-03-25 19:26 ` Philippe Mathieu-Daudé
2026-03-11 3:49 ` [PATCH v5 30/35] target/hexagon: Add cpu modes, mmu indices, next_PC to state Brian Cain
2026-03-11 3:49 ` [PATCH v5 31/35] hw/hexagon: Introduce hexagon TLB device Brian Cain
2026-03-25 19:38 ` Philippe Mathieu-Daudé
2026-03-11 3:49 ` [PATCH v5 32/35] target/hexagon: Add stubs for modify_ssr/get_exe_mode Brian Cain
2026-03-11 3:49 ` [PATCH v5 33/35] target/hexagon: Add clear_wait_mode() definition Brian Cain
2026-03-11 3:49 ` [PATCH v5 34/35] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2026-03-11 3:49 ` [PATCH v5 35/35] target/hexagon: Add hex_interrupts support Brian Cain
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